參數資料
型號: JZ48F4L0BTY
廠商: Intel Corp.
英文描述: StrataFlash Wireless Memory
中文描述: 無線的StrataFlash存儲器
文件頁數: 35/106頁
文件大?。?/td> 1272K
代理商: JZ48F4L0BTY
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
35
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
2.
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned.
2.
Figure 14.
Synchronous Single-Word Array or Non-array Read Timing
R312
R305
R304
R4
R17
R307
R15
R9
R7
R8
R303
R102
R3
R104
R106
R101
R105
R2
R306
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
Figure 15.
Continuous Burst Read, showing an Output Delay Timing
R305
R305
R305
R305
R304
R4
R7
R312
R307
R15
R303
R102
R3
R106
R105
R101
R2
R304
R304
R304
R306
R302
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
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JZ48F4L0BTZ StrataFlash Wireless Memory
JZ48F4L0QBY StrataFlash Wireless Memory
JZ48F4L0QBZ StrataFlash Wireless Memory
JZ48F4L0QTY StrataFlash Wireless Memory
JZ48F4L0QTZ StrataFlash Wireless Memory
相關代理商/技術參數
參數描述
JZ48F4L0BTZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QBY 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QBZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QTY 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory
JZ48F4L0QTZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:StrataFlash Wireless Memory