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參數(shù)資料
| 型號： | JS28F256J3A-115 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 40/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | JS28F256J3A-115 |
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256-Mbit J3 (x8/x16)
40
Datasheet
Table 18. Status Register Definitions
WSMS
ESS
ECLBS
PSLBS
VPENS
PSS
DPS
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit2
bit 1
bit 0
High Z
When
Busy
Status Register Bits
Notes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS
1 = Error in Block Erasure or Clear Lock-Bits
0 = Successful Block Erase or Clear Lock-Bits
SR.4 = PROGRAM AND SET LOCK-BIT STATUS
1 = Program Error / Error in Setting Lock-Bit
0 = Successful Program/Set Block Lock Bit
SR.3 = PROGRAMMING VOLTAGE STATUS
1 = Low Programming Voltage Detected, Operation
Aborted
0 = Programming Voltage OK
SR.2 = PROGRAM SUSPEND STATUS
1 = Program suspended
0 = Program in progress/completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit Detected, Operation Abort
0 = Unlock
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
Check STS or SR.7 to determine block erase,
program, or lock-bit configuration completion.
SR[6:0] are not driven while SR.7 = “0.”
If both SR.5 and SR.4 are “1”s after a block erase or
lock-bit configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous programming
voltage level indication. The WSM interrogates and
indicates the programming voltage level only after
Block Erase, Program, Set Block Lock-Bit, or Clear
Block Lock-Bits command sequences.
SR.1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bits only after Block Erase, Program, or
Lock-Bit configuration command sequences. It
informs the system, depending on the attempted
operation, if the block lock-bit is set. Read the block
lock configuration codes using the Read Identifier
Codes command to determine block lock-bit status.
SR0 is reserved for future use and should be
masked when polling the Status Register.
Table 19. Extended Status Register Definitions
WBS
Reserved
bit 7
Bits 6 -- 0
High Z
When
Busy
Status Register Bits
Notes
No
Yes
XSR.7 = WRITE BUFFER STATUS
1 = Write buffer available
0 = Write buffer not available
XSR.6–XSR0 = RESERVED FOR FUTURE
ENHANCEMENTS
After a Buffer-Write command, XSR.7 = 1 indicates
that a Write Buffer is available.
SR[6:0] are reserved for future use and should be
masked when polling the Status Register.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| JS28F256J3A-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| JS28F256J3A-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| JS28F256J3A-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| JS28F256J3C-110 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| JS28F256J3C-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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