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| 型號(hào)： | J-TYPE |
| 廠商： | Vectron International, Inc. |
| 英文描述： | Voltage Controlled Crystal Oscillator |
| 中文描述： | 壓控晶體振蕩器 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 135K |
| 代理商： | J-TYPE |
J-Type Voltage Controlled Crystal Oscillator
Vectron International
267 Lowell Road, Hudson, NH 03051
Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON
CMOS Output Option
3
Output Test Conditions (25±5°C) for 5 volt devices.
For 3.3V use 15pF cap only, no resistors needed.
Threshold = 1.4 volts for TTL
and 50% for CMOS
Figure 1
Output Wave Form
Figure 2
Output Test Conditions
1.024
3.686
6.144
8.448
14.318
19.44
27.000
38.880
52.000
1.544
4.000
6.176
10.000
15.360
20.000
30.000
40.000
65.536
2.000
4.032
6.312
12.000
15.440
20.480
32.000
40.960
77.760
2.048
4.096
6.400
12.288
16.000
24.000
32.768
44.736
155.520
1
3.088
4.434
8.000
12.352
16.384
24.576
34.368
50.000
3.580
5.000
8.192
13.000
18.432
24.704
35.328
51.840
Standard Frequencies, in MHz, for CMOS output option
Ordering Information for the CMOS output option (add frequency)
4
J
6 pin
Ceramic
SOJ
C
5V±10%
U
VCXO G
±50
C
0/70
A
TTL/
CMOS
45/55%
1
CMOS
45/55%
2
T Tri State
on pin 2
N
Standard
D
3.3V±10% L
±10%
linear
VCXO
N
±80
L
-40/85
J
H
±100
K
CMOS
40/60%
3
Package
Supply
Voltage
VCXO
Type
APR
(ppm)
Operating
Temp.
(°C)
Output/Duty
Cycle
Min/Max
Tri-State
Specials
1. Output is CMOS and symmetry is tested at TTL and CMOS thresholds.
2. Output is CMOS and symmetry is tested at CMOS threshold.This option is used for 3.3 V operation.
3. Output is CMOS and symmetry is tested at CMOS thresholds.This option is required for 3.3V, frequencies >51.840MHz.
4. Note: Not all combinations are possible.
Example: JDUGCKTN @ 77.76 MHz = 3.3 volt,VCXO@77.760, ±50 ppm APR, 0/70°C, 40/60% Symmetry,
CMOS,Tri-State on pin 2.
1. Uses a PLL multiplier, jitter is 25ps rms typical vs 3ps rms typical for a HFF (High Frequency Fundemental) design. Available with 5 Vdc input only.
Other frequencies available upon request.
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