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參數(shù)資料
| 型號： | ISPPAC81-01SI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ISPPAC81-01SI |
Lattice Semiconductor
ispPAC81 Data Sheet
17
Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test
mode (steady state = test). This is when the device is actually programmed, erased or veri
fi
ed. All other instructions
are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being speci
fi
cally called out (all ones and all zeroes respec-
tively). The ispPAC81 contains the required minimum instruction set as well as one from the optional instruction set.
In addition, there are several proprietary instructions that allow the device to be con
fi
gured and veri
fi
ed. For
ispPAC81, the instruction word length is
fi
ve bits. All ispPAC81 instructions available to users are shown in Table 5.
Table 5. ispPAC81 TAP Instructions
BYPASS
is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC81.
The bit code of this instruction is de
fi
ned to be all ones by the IEEE 1149.1 standard.
The required
SAMPLE/PRELOAD
instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC81 has no boundary-scan register, so for compatibility it defaults to the BYPASS mode when-
ever this instruction is received. The bit code for this instruction is de
fi
ned by Lattice as shown in Table 5.
The
EXTEST
(External Test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the Boundary-Scan Register to be connected between TDI and TDO. Again, since
the ispPAC81 has no boundary-scan logic, the device is put in the BYPASS mode to ensure speci
fi
cation compati-
bility. The bit code of this instruction is de
fi
ned by the 1149.1 standard to be all zeros.
The optional
IDCODE
(Identi
fi
cation Code) instruction is incorporated in the ispPAC81 and leaves it in its functional
mode when executed. It selects the Device Identi
fi
cation Register to be connected between TDI and TDO. The
Identi
fi
cation Register is a 32-bit shift register containing information regarding the IC manufacturer, device type
and version code (see Figure 7). Access to the Identi
fi
cation Register is immediately available, via a TAP data scan
operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction
is de
fi
ned by Lattice as shown in Table 5.
Instruction
EXTEST
ADDUSR
ABE
BBE
VERA
VERB
PRGA
PRGB
ENCAL
IDCODE
SAMPLE
BYPASS
Code
00000
00001
00010
00011
00100
00101
00110
00111
01100
01101
11110
11111
Description
External Test. Default to BYPASS.
Address User Data Register (A or B).
User A Bulk Erase.
User B Bulk Erase.
Verify User A Data Register.
Verify User B Data Register.
Program User A Data Register.
Program User B Data Register.
Enable Calibration Sequence.
Read Identi
fi
cation Data Register.
Sample/Preload. Default to BYPASS.
Bypass (Connect TDI to TDO).
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| ispPAC-CLK5304S-01T48C | 功能描述:時鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01T48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01T64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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