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參數(shù)資料
| 型號： | ISPPAC81-01SI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 176K |
| 代理商： | ISPPAC81-01SI |
Lattice Semiconductor
ispPAC81 Data Sheet
15
IEEE Standard 1149.1 Interface
Serial Port Programming Interface
Communication with the ispPAC81 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the
ispPAC81 as a serial programming interface, and not for boundary scan test purposes. There are no boundary
scan logic cells in the ispPAC81 architecture. This does not prevent the ispPAC81 from functioning correctly, how-
ever, when placed in a valid serial chain with other IEEE 1149.1 compliant devices.
A brief description of the ispPAC81 serial interface follows. For complete details of the reference speci
fi
cation, refer
to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now
includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispPAC81. The TAP controller is a state machine driven with mode and clock inputs. Under the correct protocol,
instructions are shifted into an instruction register which then determines subsequent data input, data output, and
related operations. Device programming is performed by addressing the user register, shifting data in, and then
executing a program user instruction, after which the data is transferred to internal E
2
CMOS cells. It is these non-
volatile cells that determine the con
fi
guration of the ispPAC81. By cycling the TAP controller through the necessary
states, data can also be shifted out of the user register to verify the current ispPAC81 con
fi
guration. Instructions
exist to access all data registers and perform internal control operations.
For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 speci
fi
cation.
Others are functionally speci
fi
ed, but inclusion is strictly optional. Finally, there are provisions for optional data reg-
isters de
fi
ned by the manufacturer. The two required registers are the bypass and boundary-scan registers. For
ispPAC81, the bypass register is a one-bit shift register that provides a short path through the device when bound-
ary testing or other operations are not being performed. The ispPAC81, as mentioned, has no boundary scan logic
and therefore no boundary scan register. All instructions relating to boundary scan operations place the ispPAC81
in the BYPASS mode to maintain compliance with the speci
fi
cation. The optional identi
fi
cation register described in
IEEE 1149.1 is also included in the ispPAC81. One additional data register included in the TAP of the ispPAC81 is
the Lattice de
fi
ned user register. Figure 5 shows how the instruction and various data registers are placed in an
ispPAC81.
Figure 5. ispPAC81 TAP Registers
BYPASS REGISTER
M
INSTRUCTION REGISTER
TEST ACCESS PORT
(TAP) LOGIC
ID REGISTER
USER REGISTER
TDI
TDO
TCK
TMS
OUTPUT
LATCH
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|---|---|
| ispPAC-CLK5304S-01T48C | 功能描述:時鐘驅(qū)動器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5304S-01T48I | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5304S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5304S-01T64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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