- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384545 > ISPPAC30-01PI (LATTICE SEMICONDUCTOR CORP) In-System Programmable Analog Circuit PDF資料下載
參數(shù)資料
| 型號： | ISPPAC30-01PI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 379K |
| 代理商： | ISPPAC30-01PI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁
Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
28
scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is de
fi
ned by Lattice as shown in Table 6.
Figure 12. ID Code
ispPAC30 Speci
fi
c Instructions
There are three unique address instructions speci
fi
ed by Lattice for the ispPAC30. They are ADDCFG (address
CFG), ADDCFGQ (address the CFG quick, or short register), and ADDUES (address the UES or user electronic
signature register). They all select their respective registers to be shifted into through TDI during a Shift-DR opera-
tion. Normal operation of a device is not interrupted by the execution of these instructions. They usually proceed a
program instruction (PROGCFG, or PROGUES) for putting the shifted data into E
2
con
fi
guration memory or a load
(LATCHCFG) for putting data into the device control SRAM directly. The bit codes for these instructions are found in
Table 6.
There are three unique program instructions speci
fi
ed by Lattice for the ispPAC30. They are PROGUES (program
UES), PROGCFG (program CFG), and PROGESF (program the electronic security fuse bit). The
fi
rst two store
their respective registers into E
2
con
fi
guration memory. The third, PROGESF, has no register associated with it. It
simply sets the ESF bit so shifting out CFG information is no longer possible. The only way to recover the ability to
shift out meaningful data is to reset ESF by performing a CFGBE instruction. This, of course will reset the device
con
fi
guration as well, but will keep an unauthorized user from learning the bit pattern of the device. Normal opera-
tion of the device is not interrupted during the actual programming time. A programming operation does not begin
until entry of the Run-Test/Idle state. The programming time required to insure data retention is given in the timing
speci
fi
cations. The user must ensure that the recommended programming times are observed to ensure speci
fi
ed
data retention. Note: When initially programming or reprogramming the ispPAC30 with software other than PAC-
Designer, or an authorized third-party programmer (e.g., via microcontroller), refer to the additional Lattice techni-
cal literature covering the required algorithms necessary for complete JTAG and SPI device programming control of
the ispPAC30 (speci
fi
c bit assignments, word lengths, etc.).
There are two unique load instructions speci
fi
ed by Lattice for the ispPAC30. They are the LATCHCFG (load CFG
register) and RELOADCFG (load CFG from E
2
). These instructions load the data in either the CFG register or the
stored E
2
con
fi
guration into the ispPAC30 device control SRAM. The LATCHCFG updates all or a portion of the
control SRAM, depending on whether the preceding address CFG was an ADDCFG or ADDCFGQ instruction. The
load operation does not occur until entry of the Run-Test/Idle state. Settling time for the new con
fi
guration will
depend on the con
fi
guration and time-constants of the particular circuit and can be anywhere from microseconds
to milliseconds. The actual switching to make the change, however, always occurs in less than a microsecond once
the Run-Test/Idle state is entered. The bit codes for these instructions are shown in Table 6.
There are two unique read instructions speci
fi
ed by Lattice for the ispPAC30. They are the READCFG (read CFG)
and READUES (read user electronic signature). These instructions read data out of the corresponding E
2
con
fi
gu-
ration memory into either the CFG or UES register. This is done in preparation for either an ADDCFG or ADDUES
and then a subsequent shifting out of the data in these registers. Normal operation of a device is not interrupted by
the execution of these instructions. The bit code for these instructions are shown in Table 6.
The ENCAL (enable calibration) is a unique Lattice instruction that enables the start of an auto-calibration
sequence. This operation causes both output ampli
fi
ers to go to 0V until the calibration sequence is completed
MSB
XXXX / 0000 0001 0011 0000 / 0000 0100 001 / 1
LSB
Version
E2 (4-bits)
Part Number
(16-bits)
0130h = PAC30
JEDEC Manfacturer
Identity Code for
Lattice Semiconductor
(11-bits)
Constant 1
(1-bit)
per 1149.1-1990
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC30-01S | In-System Programmable Analog Circuit |
| ISPPAC30-01SI | In-System Programmable Analog Circuit |
| ISPPAC80-01PI | In-System Programmable Analog Circuit |
| ISPPAC80-01SI | In-System Programmable Analog Circuit |
| ISPPAC81 | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC30-01S | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC80-01SI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC81 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。