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參數(shù)資料
| 型號： | ISPPAC20-01J |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | In-System Programmable Analog Circuit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大小： | 525K |
| 代理商： | ISPPAC20-01J |
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Specifications
ispPAC20
11
Theory of Operation
Introduction
The ispPAC20 includes two programmable analog mac-
rocells called PACblocks, each emulating a collection of
operational amplifiers, resistors and capacitors. Requir-
ing no external components, it flexibly implements basic
analog functions such as precision filtering, summing/
differencing, gain/attenuation and integration. Each
PACblock contains a summing amplifier, two differential
input instrument amplifiers, and an array of feedback
capacitors. The capacitors, combined with a fixed value
feedback element, provide more than 120 programmable
poles between 10kHz to 100kHz with an absolute accu-
racy of 5.0 percent. Variable gain input instrument
amplifiers make it possible to program any PACblock
gain in integer steps between
±
1 and
±
10. More complex
signal processing functions are performed by configuring
both PACblocks in combination with each other to achieve
a variety of circuit functions.
The ispPAC20 architecture is fully differential from input
to output. This effectively doubles dynamic range versus
single-ended I/O. It also affords improved performance
with regard to specifications such as input common mode
rejection (CMR) and total harmonic distortion (THD).
Differential peak-peak voltage is determined by knowing
the signal extremes on both differential input or output
pins. For example, if V(+) equals 4V and V(-) equals 1V,
the differential voltage is defined as V(+) - V(-) = Vdiff, or
4V - 1V = +3V. Since either polarity can exist on differen-
tial I/O pins, it is also possible for the opposite extreme to
exist and would mean when V(+) equals 1V and V(-)
equals 4V, the differential voltage is now 1V - 4V = -3V.
To calculate the differential peak-peak voltage or full
signal swing, the absolute difference between the two
extreme Vdiff
’
s is calculated. Using the previous ex-
amples would result in |(+3V) - (-3V)| = 6V. It can be
immediately seen that true differential signals result in a
doubling of usable dynamic range. For more explanation
of this and other differential circuit benefits, please refer
to application note AN6019.
Input polarity is programmable without affecting input
impedance or dynamic performance, since no internal
change is made other than routing to the input amplifier.
Single-ended operation is achieved by using either one
input and/or one output pin, as required, and adjusting
gain settings to achieve desired output levels.
The ispPAC20 operates on a single 5V supply and
includes an internal reference generating 2.5V. This
reference is made available externally through the volt-
age common-mode reference or VREF
OUT
pin. The
output common mode voltage is always referenced to
2.5V, regardless of the input common mode level. It is
possible, when desired, to use an externally supplied
voltage instead of VREF
OUT
, however. This optional
common-mode output voltage (V
CM
) must be provided
by the user via the CMV
IN
input pin. The only limitation is
this reference voltage must be between 1.25V and 3.25V.
When an external voltage is present, an ispPAC20 must
be programmed, on a per-PACblock basis, to use the
external reference instead of the internal 2.5V.
Configuring an ispPAC20 is accomplished using
PAC-Designer, a Windows-based design environment.
PAC-Designer includes an AC simulator for design veri-
fication prior to programming. The user can download the
design to the ispPAC20 at any time via the device
’
s IEEE
Standard 1149.1 (JTAG) compliant serial port directly
from the parallel port of a PC using an ispDOWNLOAD
cable. Once downloaded, the circuit topology and com-
ponent values are stored in non-volatile digital E
2
CMOS
cells on the ispPAC20 without any need for external
programming voltages.
Architecture
In all ispPAC products, individual programmable circuit
functions called PACells
are carefully combined to
form larger analog macrocells or PACblocks. The isp-
PAC20 has two such PACblocks that incorporate specially
configured PACells to perform amplification, summation,
integration and filtering. Each of the two filtering/summa-
tion or
“
FilSum
”
PACblocks within ispPAC20 is comprised
of three separate PACells, two input instrument amplifi-
ers and an output summing amplifier (see Figure 1). The
input amplifier PACells act as front-end gain stages for
the FilSum PACblock and allow multiple signals to be
summed together. The PACblock
’
s output amplifier is
similar to the familiar operational amplifier except that it
has true differential outputs. Also included with each
output amplifier is a filter capacitor array and switchable
DC feedback path element. These components in com-
bination enable the filtering and integrating functions of
the FilSum PACblock.
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| ISPPAC20-01JI | In-System Programmable Analog Circuit |
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| ISPPAC30-01PI | In-System Programmable Analog Circuit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ISPPAC20-01JI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC20-01TI | 功能描述:SPLD - 簡單可編程邏輯器件 Not Upgrade Device CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPPAC30 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Analog Circuit |
| ISPPAC30-01PI | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE ANALOG CIRCUIT RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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