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參數(shù)資料
| 型號： | ISPPAC-CLK5620V-01TN100C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Spot Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:530nm |
| 中文描述： | 5600 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 31/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5620V-01TN100C |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
31
Pro
fi
le Select
The ispClock5600 stores all internal con
fi
guration data in on-board E
2
CMOS memory. Up to four independent con-
fi
guration pro
fi
les may be stored in each device. The choice of which con
fi
guration pro
fi
le is to be active is speci
fi
ed
thought the pro
fi
le select inputs PS0 and PS1, as shown in Table 7.
Table 7. Profile Select Function
Each pro
fi
le controls the following internal con
fi
guration items:
M divider setting
N divider setting
V divider settings
PLL loop
fi
lter settings
Output skew settings
Internal feedback skew settings
Internal vs. external feedback selection
The following settings are independent of the selection of active pro
fi
le and will apply regardless of which pro
fi
le is
selected:
Input logic con
fi
guration
– Logic family
– Input impedance
Output bank logic con
fi
guration
– Logic family
– V-Divider signal source
– Enable/SGATE control options
– Output impedance
– Slew rate
– Signal inversion
V-Divider to be used as feedback source
Fine/Coarse skew mode selection
UES string
If any of the above items are modi
fi
ed, the change will apply across all pro
fi
les. In some cases this may cause
unanticipated behavior. If multiple pro
fi
les are used in a design, the suitability of the pro
fi
le independent settings
must be considered with respect to each of the individual pro
fi
les.
When a pro
fi
le is changed by modifying the values of the PS0 and PS1 inputs, it may be necessary to assert a
RESET signal to the ispClock5600 to restart the PLL and resynchronize all the internal dividers.
RESET and Power-up Functions
To ensure proper PLL startup and synchronization of outputs, the ispClock5600 provides both internally generated
and user-controllable external reset signals. An internal reset is generated whenever the device is powered up. An
external reset may be applied by asserting a logic HIGH at the RESET pin. Please note that the RESET pin does
not have an internal pull-up or pull-down resistor associated with it and should be tied LOW if not used. Asserting
RESET resets all internal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin
dropping. The length of time required to regain lock is related to the length of time for which RESET was asserted.
PS1
PS0
Active Pro
fi
le
0
0
Pro
fi
le 0
0
1
Pro
fi
le 1
1
0
Pro
fi
le 2
1
1
Pro
fi
le 3
相關PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5610V-01TN100I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| ISPPAC-CLK5620V-01TN100I | Backlight LED; Color:Infrared; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-CLK5610V-01TN48C | LED Ring Light; LED Color:Infrared; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:350mA; Supply Voltage:24VDC; Wavelength:880nm |
| ISPPAC-CLK5620V-01TN48C | LED Area Light; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:630nm |
| ISPPAC-CLK5610V-01TN48I | Backlight LED; Color:Red; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5620V-01TN100I | 功能描述:時鐘驅動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5620V-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-POWR1014 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014_08 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
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