參數(shù)資料
型號(hào)： ISPPAC-CLK5312S-01T48I
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 27/56頁(yè)
文件大?。?/td> 0K
描述： IC BUFFER FANOUT ISP UNIV 48TQFP
標(biāo)準(zhǔn)包裝： 250
系列： ispClock™
類型： 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL： 帶旁路
輸入： HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出： eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 267MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
Lattice Semiconductor
ispClock5300S Family Data Sheet
33
outputs in Figure 27 show how the various sources of skew error stack up in this case. Note that if two or more out-
puts are programmed to the same skew setting, then the contribution of the tSKERR skew error term does not apply.
When outputs are congured or loaded differently, this also has an effect on skew matching. If an output is set to
support a different logic type, this can be accounted for by using the t(ioo) output adders specied in the table
‘Switching Characteristics’. That table species the additional skew added to an output using SSTL, HSTL, EHSTL
as a base-line. For instance, if one output is specied as LVTTL, it has a delay adder relative to SSTL of 0.25ns. If
another output is specied as SSTL3, then one would expect 0.25ns of additional skew between the two outputs
due to this adder. This timing relationship is shown in Figure 28a.
Figure 28. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
By selecting the same feedback logic type and clock output, the output delay adders for the clock output are auto-
matically compensated for. Similarly, a reference clock delay adder can be compensated for by selecting the same
feedback input logic type and reference clock.
When the internal feedback mode is selected, however, one should add both input and output delay adders to tDELAY
specied in the Performance Characteristics PLL table to calculate the input-to-output delay.
Similarly, when one changes the slew rate of an output, the output slew rate adders (tIOS) can be used to predict
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs congured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, tIOS = 0ps), and another set to slew rate 3 (tIOS = 950ps), then one could expect
950ps of skew between the two outputs, as shown in Figure 28b.
Static Phase Offset and Input-Output Skew
The ispClock5300S’s external feedback inputs can be used to obtain near-zero effective delays from the clock ref-
erence input pins to a designated output pin. Using external feedback (Figure 29), the PLL will attempt to force the
output phase so that the rising edge phase (tφ) at the feedback input matches the rising edge phase at the refer-
ence input. The residual error between the two is specied as the static phase error. Note that any propagation
delay (tFBK) in the external feedback path drives the phase of the output signal backwards in time as measured at
the output. For this reason, if zero input-to-output delays are required, the length of the signal path between the
output pin and the feedback pin should be minimized.
SSTL3 Output
LVTTL Output
0.25ns
(a)
LVCMOS Output
(Slew rate=1)
LVCMOS Output
(Slew rate=3)
950ps
(b)
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5312S-01TN48I IC CLOCK PROGRAM BUFFER 48TQFP
VI-27Z-MX-F2 CONVERTER MOD DC/DC 2V 30W
X9317TM8I-2.7T2 IC XDCP 100TAP 100K 3WIRE 8-MSOP
X9314WST1 IC XDCP SGL 32-TAP 10K 8-SOIC
ISPPAC-CLK5316S-01T64C IC BUFFER FANOUT ISP UNIV 64TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5312S-01T48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5312S-01T64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5312S-01T64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5312S-01TN48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5312S-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*