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參數(shù)資料
| 型號： | ISPPAC-CLK5312S-01T48I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 17/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 48TQFP |
| 標準包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
24
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5300S’s ability to adjust input impedance over a range of
40Ω to 70Ω allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5300S provides multiple banks, with each bank supporting two high-speed clock outputs which are
congurable and internally terminated. There are ten banks in the ispClock5320S, eight banks in the
ispClock5316S, six banks in the ispClock5312S, four banks in the ispClock5308S and two banks in the
ispClock5304S. Programmable internal source-series termination allows the ispClock5300S to be matched to
transmission lines with impedances ranging from 40 to 70Ω. The outputs may be independently enabled or dis-
abled, either from E
2CMOS conguration or by external control lines. Additionally, each can be independently pro-
grammed to provide a xed amount of signal delay or skew, allowing the user to compensate for the effects of
unequal PCB trace lengths or loading effects. Figure 19 shows a block diagram of a typical ispClock5300S output
driver bank and associated skew control.
Because of the high edge rates which can be generated by the ispClock5300S clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 F may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
In the case where an output bank is unused, the associated VCCO pin may be either left oating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GNDO pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 19. ispClock5300S Output Driver and Skew Control
*Skew Adjust Mechanism is applicable only to outputs connected to one of the three V-Dividers and
when PLL is active (PLL-Bypass pin = 0). For all other conditions, Skew Adjust Mechanism is bypassed.
OE Control
Bank_xA
Single Ended
Output A Driver
Skew
Adjust*
From
V-Dividers
OE Control
Bank_xB
Single Ended
Output B Driver
Skew
Adjust*
From
V-Dividers
GNDO-x
VCCO-x
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5312S-01T48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01T64C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01T64I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5312S-01TN48C | 功能描述:時鐘驅動器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5312S-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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