參數(shù)資料
型號(hào): ISPPAC-CLK5308S-01TN48I
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 14/56頁(yè)
文件大?。?/td> 0K
描述: IC BUFFER FANOUT 8OUTPUT 48TQFP
標(biāo)準(zhǔn)包裝: 250
系列: ispClock™
類型: 時(shí)鐘發(fā)生器,扇出配送,零延遲緩沖器
PLL: 帶旁路
輸入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
輸出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 267MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 托盤
其它名稱: 220-1001
Lattice Semiconductor
ispClock5300S Family Data Sheet
21
Figure 14. Input Receiver Termination Conguration
Feedback input is terminated to the VTT_FBK pin through a programmable resistor.
The following usage guidelines are suggested for interfacing to supported logic families.
+
REFA_REFP
REFB_REFN
Differential
Receiver
Single-ended
Receiver
Single-ended
Receiver
To
Internal
Logic
RT
VTT_REFA
VTT_REFB
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ISPPACCLK5308S-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5308S-01TN64C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5308S-01TN64I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5312S-01T48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP Zero Delay Unv F an-Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5312S-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended