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參數資料
| 型號： | ISPLSI2096VL-165LT128 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | EE PLD, 8 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數： | 7/11頁 |
| 文件大?。?/td> | 142K |
| 代理商： | ISPLSI2096VL-165LT128 |
Specifications
ispLSI 2096VL
7
ispLSI 2096VL Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#24
20 PT
XOR Delays
Control
PTs
#33, 34,
35
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
D
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25, 26, 27
#43, 44
#36
Reset
Ded. In
#21
#29, 30,
31, 32
#38,
39
GOE 0
#42
#40, 41
0491/2032
Comb 4 PT Bypass #23
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
(0.5 + 1.1 + 3.4) + (1.2) - (0.5 + 1.1 + 1.1)
=
=
=
=
(0.5 + 1.1 + 4.1) + (2.3) - (0.5 + 1.1 + 3.4)
=
=
=
=
(0.5 + 1.1 + 4.1) + (0.3) + (1.4 + 1.6)
9.0ns
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
t
co
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
Table 2-0042/2096VL
Note: Calculations are based on timing specifications for the ispLSI 2096VL-165L.
3.5ns
3.0ns
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相關代理商/技術參數 |
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|---|---|
| ISPLSI2128 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programable High Density PLD |
| ISPLSI2128-100LM | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programable High Density PLD |
| ISPLSI2128-100LMI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programable High Density PLD |
| ISPLSI2128-100LQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPLSI2128-100LQI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programable High Density PLD |
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