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參數(shù)資料
| 型號： | ISPLSI2032E-225LT48 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | EE PLD, 5.5 ns, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 173K |
| 代理商： | ISPLSI2032E-225LT48 |
Specifications
ispLSI 2032E
7
U-ES
Over Recommended Operating Conditions
Internal Timing Parameters
1
t
io
t
din
GRP
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2032E
Inputs
UNITS
-200
MIN.
-180
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
21 Dedicated Input Delay
–
–
–
–
0.6
1.3
ns
ns
t
grp
GLB
t
4ptbpc
t
4ptbpr
22 GRP Delay
–
–
0.7
ns
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
Outputs
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
28 GLB Register Bypass Delay
–
–
–
–
–
–
–
–
3.8
3.8
3.8
0.0
ns
ns
ns
ns
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
–
–
0.3
2.7
–
–
ns
ns
31 GLB Register Clock to Output Delay
–
–
0.7
ns
3
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
–
–
–
–
–
–
1.1
2.9
5.9
3.7
ns
ns
ns
ns
1.5
t
ob
t
sl
t
oen
t
odis
t
goe
Clocks
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
–
–
–
–
1.3
1.5
ns
ns
0.4
1.3
0.7
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
–
–
–
1.8
2.8
ns
ns
2.8
2.8
2.8
0.0
1.8
0.8
1.7
0.7
2.9
2.5
4.4
3.2
0.7
36 ORP Delay
37 ORP Bypass Delay
–
–
–
–
1.1
0.6
ns
ns
1.0
0.0
0.6
1.5
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
–
–
–
–
–
2.8
2.8
2.2
ns
ns
ns
1.5
1.5
t
gy0
t
gy1/2
Global Reset
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.2
1.4
1.4
1.6
1.4
1.6
ns
ns
1.2
1.4
t
gr
45 Global Reset to GLB
–
–
3.5
ns
2.7
-225
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
1.3
0.7
–
–
2.2
2.2
2.2
0.0
1.2
1.2
0.8
1.7
0.7
1.3
2.5
4.2
2.8
0.3
–
–
1.0
0.0
1.0
1.5
–
–
–
1.5
1.5
2.0
0.8
1.0
0.8
1.0
–
2.7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IspLSI2032E-180LJ44 | In-System Programmable SuperFAST High Density PLD |
| ISPLSI2032E-180LT44 | In-System Programmable SuperFAST⑩ High Density PLD |
| IspLSI2032E-180LT44 | In-System Programmable SuperFAST High Density PLD |
| ISPLSI2032E-225LJ44 | Solderless Terminal RoHS Compliant: Yes |
| IspLSI2032E-225LJ44 | In-System Programmable SuperFAST High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032LV60LJ | 制造商:LATTICE 功能描述:New |
| ISPLSI2032LV-60LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2032LV-60LJI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2032LV-60LT44 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2032LV-60LT44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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