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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ISPLSI 2128E-100LT176 |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 11/11闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PLD ISP 128I/O 10NS 176TQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 40 |
| 绯诲垪锛� | ispLSI® 2000E |
| 鍙法绋嬮鍨嬶細 | 绯荤当(t菕ng)鍏�(n猫i)鍙法绋� |
| 鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� | 10.0ns |
| 闆诲闆绘簮 - 鍏�(n猫i)閮細 | 4.75 V ~ 5.25 V |
| 閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 | 32 |
| 瀹忓柈鍏冩暩(sh霉)锛� | 128 |
| 闁€鏁�(sh霉)锛� | 6000 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 128 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 176-LQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 176-TQFP锛�24x24锛� |
| 鍖呰锛� | 鎵樼洡 |
| 鍏跺畠鍚嶇ū锛� | ISPLSI2128E-100LT176 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)鐣�(d膩ng)鍓嶇11闋�(y猫)
Specifications ispLSI 2128E
9
Pin Description
Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all
the GLBs on the device.
Active Low (0) Reset pin which resets all of the GLB registers in the device.
Input - Dedicated in-system programming enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK options become active.
Input - This pin performs two functions. When
BSCAN is logic low, it functions as an input
pin to load programming data into the device. SDI is also used as one of the two control
pins for the ISP state machine. When
BSCAN is high, it functions as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
NAME
Table 2-0002/2128E
DESCRIPTION
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
Global Output Enable input pins.
GOE 0, GOE 1
RESET
Y0, Y1, Y2
BSCAN
TDI/IN 71
TCK/IN 01
TMS/IN 11
TDO/IN 61
Output/Input - This pin performs two functions. When
BSCAN is logic low, it functions as
the pin to read the isp data. When
BSCAN is high, it functions as a dedicated input pin.
Input - This pin performs two functions. When
BSCAN is logic low, it functions as pin to
control the operation of the programming state machine. When
BSCAN is high, it
functions as a dedicated input pin.
Input - This pin performs two functions. When
BSCAN is logic low, it functions as a clock
pin for the Serial Shift Register. When
BSCAN is high, it functions as a dedicated input pin.
Ground (GND)
GND
V
VCC
TQFP PIN NUMBERS
27,
35,
41,
46,
52,
59,
65,
71,
77,
83,
90,
95,
102,
116,
124,
130,
135,
141,
148,
154,
160,
167,
173,
3,
8,
16,
28,
36,
42,
47,
53,
60,
66,
72,
79,
85,
91,
96,
103,
119,
125,
131,
136,
143,
149,
155,
161,
168,
174,
4,
9,
17,
31,
37,
43,
48,
55,
61,
67,
73,
80,
86,
92,
97,
104,
120,
126,
132,
138,
145,
150,
156,
163,
169,
175,
5,
12,
18
32,
38,
44,
50,
57,
62,
68,
75,
81,
87,
93,
99,
105,
121,
127,
133,
139,
146,
151,
158,
164,
170,
176,
6,
14,
33,
39,
45,
51,
58,
63,
70,
76,
82,
88,
94,
101,
115,
123,
129,
134,
140,
147,
153,
159,
165,
171,
2,
7,
15,
22
23
24
25
26
114
1,
64,
117,
172
11,
69,
128,
29,
84,
137,
19, 21,
111
110, 109,
40,
89,
152,
106, 107, 112, 113
49,
108,
157,
13,
122,
34,
144,
56,
166
78,
100,
CC
Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be connected to the
same voltage level.
VCCIO
10,
118,
No Connect
NC
1. Pins have dual function capability.
20
30,
142,
54,
162
74,
98,
Dedicated input pins to the device.
IN 2 - IN 5
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| EEC07DRYH | CONN EDGECARD 14POS DIP .100 SLD |
| RSC35DRAS | CONN EDGECARD 70POS R/A .100 SLD |
| RMC35DRAS | CONN EDGECARD 70POS R/A .100 SLD |
| RBB120DHNN | CONN EDGECARD 240PS DIP .050 SLD |
| ISPLSI 1048EA-100LQ128 | IC PLD ISP 96I/O 10NS 128PQFP |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISPLSI2128E-100LT176 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
| ISPLSI2128E-135LT176 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
| ISPLSI2128E-165LT176 | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Electrically-Erasable Complex PLD |
| ISPLSI2128E-180LT176 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤炲瀷:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
| ISPLSI2128V | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:3.3V High Density Programmable Logic |
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