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參數(shù)資料
| 型號(hào)： | ISPGDS14-7J |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | in-system programmable Generic Digital SwitchTM |
| 中文描述： | EE PLD, 7.5 ns, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 104K |
| 代理商： | ISPGDS14-7J |
Specifications
ispGDS
4
Device Programming
The ispGDS family of devices uses a standard JEDEC file, as
used for programmable logic devices, to describe device pro-
gramming information. Popular logic compilers, such as ABEL
and CUPL, can produce the JEDEC files for these devices.
The JEDEC files can be used to program the ispGDS devices in
a number of ways, which are shown in the section titled ISP
Architecture and Programming.
Electronic Signature
An electronic signature word is provided with every ispGDS
device. It contains 32 bits of reprogrammable memory that can
contain user defined data. Some uses include user ID codes,
revision numbers, or inventory control.
NOTE: The electronic signature is included in checksum
calculations. Changing the electronic signature will alter the
fuse checksum in the JEDEC fusemap.
ispGDS Family Overview
There are three members of the ispGDS family, the ispGDS22,
ispGDS18, and ispGSD14. The numerical portion of the part
name indicates the number of I/O cells available. All of the
devices are available in a DIP package, with the ispGDS22 and
ispGDS14 also available in a PLCC package. Each of the
devices operate identically, with the only difference being the
number of I/O cells available.
The ispGDS devices are all programmed through a four-pin
interface, using TTL level signals. The four dedicated program-
ming pins are named MODE, SDI, SDO, and SCLK. No high-
voltage is needed, as the voltages needed for programming are
generated internally. Programming of the entire device, includ-
ing erasure, can be done in less than one second. During the
programming operation, all I/O pins will be tri-stated. Further
details of the programming process can be found in the In-
System Programming section later in this datasheet.
The I/O cells in each device are divided equally into two banks
(Bank A and Bank B). Each I/O cell can be configured as an
input, an inverting output, a non-inverting output, or set to a fixed
TTL high or low. A switch matrix connects the I/O banks,
allowing an I/O cell in one bank to be connected to any of the I/
O cells in the other bank. A single I/O cell configured as an input
can drive one or more I/O cells in the other bank. The full I/O
macrocell, which is identical for each of the I/O pins, is shown
below. The allowable configurations are shown on the following
page.
In-System Programmability
The ispGDS family of devices feature In-System Programmable
technology. By integrating all the high voltage programming
circuitry on-chip, programming can be accomplished by simply
shifting data into the device. Once the function is programmed,
the non-volatile E
2
CMOS cells will not lose the pattern even
when the power is turned off.
All necessary programming is done via four TTL level logic
interface signals. These four signals are fed into the on-chip
programming circuitry where a state machine controls the
programming. The interface signals are Serial Data In (SDI),
Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE)
control. For details on the operation of the internal state
machine and programming of ispGDS devices please refer to
the ISP Architecture and Programming section in this Data
Book.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPGDS14-7P | in-system programmable Generic Digital SwitchTM |
| ISPGDS18-7P | in-system programmable Generic Digital SwitchTM |
| ISPGDS22 | in-system programmable Generic Digital SwitchTM |
| ISPGDS22-7J | in-system programmable Generic Digital SwitchTM |
| ISPGDS22-7P | in-system programmable Generic Digital SwitchTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDS14-7P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPGDS18-7P | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ISPGDS22 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:in-system programmable Generic Digital SwitchTM |
| ISPGDS22-7J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispGDX2 DIGITAL SWITCH RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPGDS22-7P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:in-system programmable Generic Digital SwitchTM |
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