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參數(shù)資料
| 型號： | ISPGDS18-7P |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | in-system programmable Generic Digital SwitchTM |
| 中文描述： | EE PLD, 7.5 ns, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 104K |
| 代理商： | ISPGDS18-7P |
ispGDS22/18/14
in-system programmable
Generic Digital Switch
TM
Features
HIGH-SPEED SWITCH MATRIX
— 7.5 ns Maximum Propagation Delay
— Typical Icc = 25 mA
— UltraMOS
Advanced CMOS Technology
FLEXIBLE I/O MACROCELL
— Any I/O Pin Can be Input, Output, or Fixed
TTL High or Low
— Programmable Output Polarity
— Multiple Outputs Can be Driven by One Input
IN-SYSTEM PROGRAMMABLE (5-VOLT ONLY)
— Programming Time of Less Than One Second
— 4-Wire Programming Interface
— Minimum 10,000 Program/Erase Cycles
E
2
CELL TECHNOLOGY
— Non-Volatile Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
APPLICATIONS INCLUDE:
— Software-Driven Hardware Configuration
— Multiple DIP Switch Replacement
— Software Configuration of Add-In Boards
— Configurable Addressing of I/O Boards
— Multiple Clock Source Selection
— Cross-Matrix Switch
ELECTRONIC SIGNATURE FOR IDENTIFICATION
The Lattice Semiconductor ispGDS family is an ideal solution
for reconfiguring system signal routing or replacing DIP switches
used for feature selection. With today’s demands for customer
ease of use, there is a need for hardware which is easily
reconfigured electronically without dismantling the system. The
ispGDS devices address this challenge by replacing conventional
switches with a software configurable solution. Since each I/O pin
can be set to an independent logic level, the ispGDS devices can
replace most DIP switch functions with about half the pin count,
and without the need for additional pull-up resistors. In addition
to DIP switch replacement, the ispGDS devices are useful as
signal routing cross-matrix switches. This is the only non-volatile
device on the market which can provide this flexibility.
With a maximum tpd of 7.5ns, and a typical active Icc of only 25
mA, these devices provide maximum performance at very low
power levels. The ispGDS devices may be programmed in-sys-
tem, using 5 volt only signals, through a simple 4-wire program-
ming interface. The ispGDS devices are manufactured using
Lattice Semiconductor’s advanced non-volatile E
2
CMOS process
which combines CMOS with Electrically Erasable (E
2
) floating gate
technology. High speed erase times (
<
100ms) allow the devices
to be reprogrammed quickly and efficiently.
Each I/O macrocell can be configured as an input, an inverting
or non-inverting output, or a fixed TTL high or low output. Any
I/O pin can be driven by any other I/O pin in the opposite bank.
A single input can drive one or more outputs in the opposite bank,
allowing a signal (such as a clock) to be distributed to multiple des-
tinations on the board, under software control. The I/Os accept
and drive TTL voltage levels.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
Lattice Semiconductor is able to deliver 100% field programma-
bility and functionality of all Lattice Semiconductor
products. In
addition, 10,000 erase/write cycles and data retention in excess
of 20 years are specified.
PROGRAMMABLE
SWITCH MATRIX
Bank B
B
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I/O Cell
I
I
I
I
I
I
I
I
I
I
I
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B
B
B
B
B
B
B
B
B
B
B
Vcc
C0
C1
C2
Switch
Matrix
0 1
1 0
1 1
0 0
4:1 MUX
Closed only when C0=1 and C1=0
I/O Cell
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268--8037; http://www.latticesemi.com
July 1997
ispgds_02
Functional Block Diagram (ispGDS22)
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPGDS22 | in-system programmable Generic Digital SwitchTM |
| ISPGDS22-7J | in-system programmable Generic Digital SwitchTM |
| ISPGDS22-7P | in-system programmable Generic Digital SwitchTM |
| ISPGDX160VA-7B208 | In-System Programmable 3.3V Generic Digital CrosspointTM |
| ISPGDX160VA-3B208 | In-System Programmable 3.3V Generic Digital CrosspointTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDS22 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:in-system programmable Generic Digital SwitchTM |
| ISPGDS22-7J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Use ispGDX2 DIGITAL SWITCH RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPGDS22-7P | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:in-system programmable Generic Digital SwitchTM |
| ISPGDX | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Generic Digital Crosspoint |
| ISPGDX120A-5Q160 | 功能描述:模擬和數(shù)字交叉點 IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
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