參數(shù)資料
型號(hào): ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁(yè)數(shù): 20/62頁(yè)
文件大?。?/td> 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
20 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
In the DACK-only mode, the ISP1183 uses the DACK signal as data strobe. Input
signals RD_N and WR_N are ignored. This mode is used in CPU systems that have a
single address space for memory and I/O access. Such systems have no separate
MEMW_N and MEMR_N signals: the RD_N and WR_N signals are also used as
memory data strobes.
11.4 End-Of-Transfer conditions
11.4.1
Bulk endpoints
A DMA transfer to or from a bulk endpoint can be terminated by any of the following
conditions (for bit names, refer to the DMA Configuration register in
Table 32
):
The DMA transfer completes as programmed in the DMA Counter register
(CNTREN = 1)
A short packet is received on an enabled OUT endpoint (SHORTP = 1)
DMA operation is disabled by clearing bit DMAEN.
DMA Counter register:
An EOT from the DMA Counter register is enabled by setting
bit CNTREN in the DMA Configuration register. The ISP1183 has a 16-bit DMA
Counter register, which specifies the number of bytes to be transferred. When DMA is
enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the
DMA Counter register. When the internal counter completes the transfer as
programmed in the DMA counter, an EOT condition is generated and the DMA
operation stops.
Short packet:
Normally, the transfer byte count must be set though a control
endpoint before any DMA transfer occurs. When a short packet has been enabled as
EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a
short packet in the data. This mechanism permits the use of a fully autonomous data
transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token
will stop the DMA operation after transferring the data bytes of this packet.
Fig 10. ISP1183 in the DACK-only DMA mode.
RAM
ISP1183
DMA
CONTROLLER
CPU
DREQ
DACK
HRQ
HLDA
HRQ
HLDA
DREQ_N
DACK_N
RD_N
WR_N
004aaa292
DATA[7:0]
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