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| 型號： | ISP1181 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件) |
| 中文描述： | 全速通用串行總線接口設(shè)備（全速通用串行總線接口器件） |
| 文件頁數(shù)： | 33/69頁 |
| 文件大小： | 1655K |
| 代理商： | ISP1181 |
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Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
33 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
Remark:
There is no protection against writing or reading past a buffer’s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer are only
meaningful after a successful transaction. Exception: during DMA access of a
double-buffered endpoint, the buffer pointer automatically points to the secondary
buffer after reaching the end of the primary buffer.
12.2.2
Write/Read Endpoint Status
This command is used to read the status of the endpoint FIFO or stall the endpoint by
writing. The command accesses the Endpoint Status Register, the bit allocation of
which is shown in
Table 33
.
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microcontroller can re-stall it with the Write Endpoint Status command.
Table 30: Endpoint FIFO organization
Byte #
(8-bit bus)
(16-bit bus)
0
0 (lower byte)
1
0 (upper byte)
2
1 (lower byte)
3
1 (upper byte)
..
..
(N
+
1)
M = (N + 1) DIV 2
Word #
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
..
data byte N
Table 31: Example of endpoint FIFO access (8-bit bus width)
A0
Phase
Bus lines
1
command
D[7:0]
0
data
D[7:0]
0
data
D[7:0]
0
data
D[7:0]
0
data
D[7:0]
0
data
D[7:0]
0
data
D[7:0]
..
..
..
Byte #
-
0
1
2
3
4
5
..
Description
command code (00H to 1FH)
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte 3
data byte 4
..
Table 32: Example of endpoint FIFO access (16-bit bus width)
A0
Phase
Bus lines
1
command
D[7:0]
D[15:8]
0
data
D[15:0]
0
data
D[15:0]
0
data
D[15:0]
..
..
..
Word #
-
-
0
1
2
..
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
..
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