參數(shù)資料
型號: ISP1181
廠商: NXP Semiconductors N.V.
英文描述: Full-speed Universal Serial Bus Interface Device(全速通用串行總線接口器件)
中文描述: 全速通用串行總線接口設(shè)備(全速通用串行總線接口器件)
文件頁數(shù): 23/69頁
文件大小: 1655K
代理商: ISP1181
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
23 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
12. Commands and registers
The functions and registers of ISP1181 are accessed via commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
Table 15
.
A complete access consists of two phases:
1.
Command phase
: when address bit A0 = 1, the ISP1181 interprets the data on
the lower byte of the bus (bits D7 to D0) as a command code. Commands without
a data phase are executed immediately.
2.
Data phase (optional)
: when address bit A0 = 0, the ISP1181 transfers the data
on the bus to or from a register or endpoint FIFO. Multi-byte registers are
accessed least significant byte/word first.
The following applies for register or FIFO access in 16-bit bus mode:
The upper byte (bits D15 to D8) in command phase or the undefined byte in data
phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is
not
transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the firmware. The packet length is
stored in the first 2 bytes of the endpoint buffer.
Table 15: Command and register summary
Name
Initialization commands
Write Control OUT Configuration
Destination
Code (Hex)
Transaction
[1]
Endpoint Configuration Register
endpoint 0 OUT
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Endpoint Configuration Register
endpoint 0 OUT
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Address Register
Mode Register
20
write 1 byte/word
[6]
Write Control IN Configuration
21
write 1 byte/word
[6]
Write Endpoint n Configuration
(n = 1 to 14)
Read Control OUT Configuration
22 to 2F
write 1 byte/word
[6] [3]
30
read 1 byte/word
[6]
Read Control IN Configuration
31
read 1 byte/word
[6]
Read Endpoint n Configuration
(n = 1 to 14)
Write/Read Device Address
Write/Read Mode Register
Write/Read Hardware Configuration Hardware Configuration Register
Write/Read Interrupt Enable
Register
Write/Read DMA Configuration
Write/Read DMA Counter
Reset Device
32 to 3F
read 1 byte/word
[6]
B6/B7
B8/B9
BA/BB
C2/C3
write/read 1 byte/word
[6]
write/read 1 byte/word
[6]
write/read 1 byte/word
[6]
write/read 4 bytes
Interrupt Enable Register
DMA Configuration Register
DMA Counter Register
resets all registers
F0/F1
F2/F3
F6
write/read 1 byte/word
[6]
write/read 2 bytes
none
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