參數(shù)資料
型號: ISP1161A1BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 98/127頁
文件大?。?/td> 2762K
代理商: ISP1161A1BD
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
98 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
14.2.3
Stall Endpoint/Unstall Endpoint
These commands are used to stall or unstall an endpoint. The commands modify the
content of the Endpoint Status Register (see
Table 91
).
A stalled control endpoint is automatically unstalled when it receives a SETUP token,
regardless of the packet content. If the endpoint should stay in its stalled state, the
microprocessor can re-stall it with the Stall Endpoint command.
When a stalled endpoint is unstalled (either by the Unstall Endpoint command or by
receiving a SETUP token), it is also re-initialized. This flushes the buffer: in and if it is
an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.
Code (Hex): 40 to 4F —
stall (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 80 to 8F —
unstall (control OUT, control IN, endpoint 1 to 14)
Transaction —
none
14.2.4
Validate Endpoint Buffer
This command signals the presence of valid data for transmission to the USB host, by
setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in
the buffer is valid and can be sent to the host, when the next IN token is received. For
a double-buffered endpoint this command switches the current FIFO for CPU access.
Remark:
For special aspects of the control IN endpoint see
Section 11.3.6
.
Code (Hex): 61 to 6F —
validate endpoint buffer (control IN, endpoint 1 to 14)
Transaction —
none
14.2.5
Clear Endpoint Buffer
This command unlocks and clears the buffer of the selected OUT endpoint, allowing
the reception of new packets. Reception of a complete packet causes the Buffer Full
flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a
NAK condition, until the buffer is unlocked using this command. For a double-buffered
endpoint this command switches the current FIFO for CPU access.
Remark:
For special aspects of the control OUT endpoint see
Section 11.3.6
.
Code (Hex): 70, 72 to 7F —
clear endpoint buffer (control OUT, endpoint 1 to 14)
Transaction —
none
14.2.6
Check Endpoint Status
This command is used to check the status of the selected endpoint FIFO without
clearing any status or interrupt bits. The command accesses the Endpoint Status
Image Register, which contains a copy of the Endpoint Status Register. The bit
allocation of the Endpoint Status Image Register is shown in
Table 93
.
Code (Hex): D0 to DF —
check status (control OUT, control IN, endpoint 1 to 14)
Transaction —
write/read 1 word
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