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參數(shù)資料
| 型號： | ISLA222P20IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL/SPI 72QFN |
| 標準包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 830mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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ISLA222P
16
FN7853.1
June 17, 2011
Theory of Operation
Functional Description
The ISLA222P is based on a 12-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(see Figure 20). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully:
A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
DNC pins must not be connected
SDO has an internal pull-up and should not be driven externally
RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized, the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 19. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 250MSPS the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
FIGURE 19. CALIBRATION TIMING
CLKP
CLKN
CLKOUTP
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
CALIBRATION
TIME
RESETN
CAL_STATUS
BIT
FIGURE 20. A/D CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5- BIT
FLASH
6- STAGE
1.5- BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3- BIT
FLASH
LVDS/LVCMOS
OUTPUTS
+
–
FLASH
2.5-BIT
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISLA222P25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA222P25IRZ | 制造商:Intersil Corporation 功能描述:12-BIT 250MSPS DUAL ADC, 72-PIN QFN - Trays 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SRL/SPI 72QFN 制造商:Intersil 功能描述:12-BIT 250MSPS DL AD C 72-PIN |
| ISLA222S | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 12-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC |
| ISLA222S12 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 14-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC |
| ISLA222S12IR1Z | 制造商:Intersil Corporation 功能描述:DUAL 12-BIT, 125MSPS ADC W/HIGH SPEED SERIAL JESD204B OUTPUT - Trays 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SPI/SRL 125M 48LQFN |
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