參數(shù)資料
型號(hào): ISL97653AIRZ
廠商: INTERSIL CORP
元件分類: 顯示驅(qū)動(dòng)器
英文描述: 5-Channel Integrated LCD Supply
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PQCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, PLASTIC, QFN-40
文件頁數(shù): 9/18頁
文件大小: 523K
代理商: ISL97653AIRZ
9
FN6367.0
December 6, 2007
FIGURE 13. BOOST CURRENT LIMIT
FIGURE 14. BUCK CURRENT LIMIT
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
PVIN2
Logic buck supply voltage. This is also the analog supply from which the VL is generated. Needs at
least 1μF bypassing.
2
CB
Logic buck boot strap pin. Generate the gate drive voltage for the N-Channel MOSFET by connecting
a 1μF cap to the switching node LXL1,2.
3, 4
LXL1, 2
Logic buck switching node. Source of the high side internal power N-Channel MOSFET for the Buck.
5, 6
PGND3,4
Logic buck ground pin.
7
CM2
Buck compensation pin. An RC network is recommended. Increase R for better transient response at
the expense of stability.
8
FBL
Logic buck feedback pin. High impedance input to regulate at 1.215V.
9
VL
5.25V internal regulator output. Bypass with a 4.7μF cap. Ref voltage is generated from VL.
10
VREF
Reference voltage output. Bypass with a low valued cap for transients - recommend 220nF. Should not
be greater than 5 times CDEL cap to ensure correct start-up sequence.
11
FBN
Negative charge pump feedback pin. High impedance input to regulate to 0.203V.
12
SUPN
Negative charge pump supply voltage. Can be the same as or different from A
VDD.
13
NOUT
Negative charge pump driver output.
14
PGND5
Charge pump ground pin.
15
C1P
Charge pump capacitor 1, positive connection.
16
C1N
Charge pump capacitor 1, negative connection.
17
C2P
Charge pump capacitor 2, positive connection.
18
C2N
Charge pump capacitor 2, negative connection.
19
SUPP
Positive charge pump supply. Can be the same as or different from A
VDD.
20
FBP
Positive charge pump feedback pin. High impedance input to regulate at 1.215V
21
POUT
V
ON
charge pump output.
22
COM
High voltage switch control output. V
ON
slice output.
23
DRN
Lower reference voltage for V
ON
slice output. Usually connected to A
VDD
.
24
CTL
Input control pin for V
ON
slice output.
Typical Performance Curves
(Continued)
Ch1 = LXL (400ns/DIV)
Ch2 = ILXL (400ns/DIV)
Ch1 = LXL (400ns/DIV)
Ch2 = ILXL (400ns/DIV)
ISL97653A
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