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參數(shù)資料
| 型號： | ISL9208IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Multi-Cell Li-ion Battery Pack OCP/Analog Front End |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-2, QFN-32 |
| 文件頁數(shù)： | 9/29頁 |
| 文件大?。?/td> | 495K |
| 代理商： | ISL9208IRZ |
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9
FN6446.0
February 16, 2007
SERIAL INTERFACE CHARACTERISTICS
(OVER RECOMMENDED OPERATING CONDITIONS UNLESS OTHERWISE SPECIFIED)
SCL Clock Frequency
f
SCL
100
kHz
Pulse Width Suppression Time at SDA
and SCL Inputs
t
IN
Any pulse narrower than the max spec is
suppressed.
50
ns
SCL Falling Edge to SDA Output Data
Valid
t
AA
From SCL falling crossing V
IH
(min), until
SDA exits the V
IL
(max) to V
IH
(min) window.
3.5
μs
Time the Bus Must Be Free Before Start
of New Transmission
t
BUF
SDA crossing V
IH
(min) during a STOP
condition to SDA crossing V
IH
(min) during
the following START condition.
4.7
μs
Clock Low Time
t
LOW
Measured at the V
IL
(max) crossing.
4.7
μs
Clock High Time
t
HIGH
Measured at the V
IH
(min) crossing.
4.0
μs
Start Condition Setup Time
t
SU:STA
SCL rising edge to SDA falling edge. Both
crossing the V
IH
(min) level.
4.7
μs
Start Condition Hold Time
t
HD:STA
From SDA falling edge crossing V
IL
(max) to
SCL falling edge crossing V
IH
(min).
4.0
μs
Input Data Setup Time
t
SU:DAT
From SDA exiting the V
IL
(max) to V
IH
(min)
window to SCL rising edge crossing V
IL
(min).
250
ns
Input Data Hold Time
t
HD:DAT
From SCL rising edge crossing V
IH
(min) to
SDA entering the V
IL
(max) to V
IH
(min)
window.
0
μs
Stop Condition Setup Time
t
SU:STO
From SCL rising edge crossing V
IH
(min) to
SDA rising edge crossing V
IL
(max).
4.0
μs
Stop Condition Hold Time
t
HD:STO
From SDA rising edge to SCL falling edge.
Both crossing V
IH
(min).
4.0
μs
Data Output Hold Time
t
DH
From SCL falling edge crossing V
IL
(max)
until SDA enters the V
IL
(max) to V
IH
(min)
window. (Note 4)
300
ns
SDA and SCL Rise Time
t
R
From V
IL
(max) to V
IH
(min).
1000
ns
SDA and SCL Fall Time
t
F
From V
IH
(min) to V
IL
(max).
300
ns
Capacitive Loading Of SDA Or SCL
Cb
Total on-chip and off-chip
400
pF
SDA and SCL Bus Pull-up Resistor-
Off Chip
R
OUT
Maximum is determined by t
R
and t
F
.
For C
B
= 400pF, max is about 2~2.5k
Ω
For C
B
= 40pF, max is about 15k
Ω
to 20k
Ω
1
k
Ω
Input Leakage Current (SCL, SDA)
I
LI
-10
10
μA
Input Buffer Low Voltage (SCL, SDA)
V
IL
Voltage relative to V
SS
of the device.
-0.3
V
RGO
x 0.3
V
Input Buffer High Voltage (SCL, SDA)
V
IH
Voltage relative to V
SS
of the device.
V
RGO
x 0.7
V
RGO
+ 0.1V
V
Output Buffer Low Voltage (SDA)
V
OL
I
OL
= 1mA
0.4
V
SDA and SCL Input Buffer Hysteresis
I
2
CHYST Sleep bit = 0
0.05 * V
RGO
V
NOTE:
3. Power up of the device requires all V
CELL1
, V
CELL2
, V
CELL3
, and VCC to be above the limits specified.
4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
5. Typical +125°C ±10%, based on design and characterization data.
6. Typical 5
Ω
±2
Ω
, based on design and characterization data.
7. Maximum output capacitance = 15pF.
Operating Specifications
Over the recommended operating conditions unless otherwise specified
(Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNIT
ISL9208
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