參數(shù)資料
型號: ISL9208IRZ
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Multi-Cell Li-ion Battery Pack OCP/Analog Front End
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-2, QFN-32
文件頁數(shù): 18/29頁
文件大?。?/td> 495K
代理商: ISL9208IRZ
18
FN6446.0
February 16, 2007
.
Device Description
Design Theory
Instructed by the microcontroller, the ISL9208 performs cell
voltage monitoring and cell balancing operations,
overcurrent and short circuit monitoring with automatic pack
shutdown using built-in selectable time delays, and
automatic turn off of the power FETs and cell balancing FETs
in an over-temperature condition. All automatic functions of
the ISL9208 can be turned off and the microcontroller can
manage the operations through software.
Battery Connection
The ISL9208 supports packs of 5 to 7 series connected
Li-ion cells. Connection guidelines for each cell combination
are shown in Figure 1.
System Power Up/Power Down
The ISL9208 powers up when the voltages on V
CELL1
,
V
CELL2
, V
CELL3
, and VCC all exceed their POR threshold.
At this time, the ISL9208 wakes up and turns on the RGO
output.
RGO provides a regulated 3.3VDC ±10% voltage at pin
RGO. It does this by using a control voltage on the RGC pin
to drive an external NPN transistor (See Figure 2.) The
transistor should have a beta of at least 70 to provide ample
current to the device and external circuits and should have a
V
CE
of greater than 30V (preferably 50V). The voltage at the
emitter of the NPN transistor is monitored and regulated to
3.3V volts by the control signal RGC. RGO also powers most
of the ISL9208 internal circuits. A 500
Ω
resistor is
recommended in the collector of the NPN transistor to
minimize initial current surge when the regulator turns on.
Once powered up, the device remains in a wake up state
until put to sleep by the microcontroller (typically when the
cells drop too low in voltage) or until the V
CELL1
, V
CELL2
,
V
CELL3
, or VCC voltages drop below their POR threshold.
TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H)
BIT
FUNCTION
DESCRIPTION
7
FSETEN
Enable discharge set writes
When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the Feature
Set register (Addr: 07H). Default on initial power up is “0”.
6
CHSETEN
Enable charge set writes
When set to “1”, allows writes to the Charge Set register. When set to “0”, prevents writes to the Feature
Set register (Addr: 06H). Default on initial power up is “0”.
5
DISSETEN
Enable discharge set writes
When set to “1”, allows writes to the Discharge Set register (Addr: 05H). When set to “0”, prevents writes
to the Feature Set register. Default on initial power up is “0”.
4
UFLG3
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO
turns off.
3
UFLG2
User Flag 3
General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO
turns off.
2
RESERVED
Reserved for future expansion.
1
RESERVED
Reserved for future expansion.
0
RESERVED
Reserved for future expansion.
VCELL7
VCELL6
VCELL5
VCELL4
VCELL3
VCELL2
VCELL1
VSS
7 CELLS
VCELL7
VCELL6
VCELL5
VCELL4
VCELL3
VCELL2
VCELL1
VSS
6 CELLS
VCELL7
VCELL6
VCELL5
VCELL4
VCELL3
VCELL2
VCELL1
VSS
5 CELLS
FIGURE 1. BATTERY CONNECTION OPTIONS
Note: Multiple cells can be connected in parallel
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB7
CB6
CB5
CB4
CB3
CB2
CB1
RGC
RGO
VSS
VCC
3.3V
GND
FIGURE 2. VOLTAGE REGULATOR CIRCUITS
500
ISL9208
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