參數(shù)資料
型號: ISL9203ACRZ
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Li-ion/Li Polymer Battery Charger
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10
封裝: 3 X 3 MM, ROHS COMPLIANT, PLASTIC, DFN-10
文件頁數(shù): 13/14頁
文件大小: 320K
代理商: ISL9203ACRZ
13
FN6430.0
February 14, 2007
Input and Output Capacitor Selection
Due to the inductance of the power leads of the wall adapter
or USB source, the input capacitor type must be properly
selected to prevent high voltage transient during a hot-plug
event. A tantalum capacitor is a good choice for its high
ESR, providing damping to the voltage transient. Multi-layer
ceramic capacitors, however, have a very low ESR and
hence when chosen as input capacitor, a 1
Ω
series resistor
must be used, as shown in the Typical Applications Section,
to provide adequate damping.
The output capacitor can be any ceramic type with the value
higher than 0.1μF. However, if there is a chance the charger
will be used as an LDO linear regulator, a 10μF tantalum
capacitor is recommended. Note that the charger always
steps through the 15-cycle V
MIN
verification time before the
charge current rises to the constant charge current, as
discussed earlier. Hence, when using as an LDO, the
system should make sure not to load the charger heavily
until the 15-cycle verification is completed.
Working with Current-Limited Adapter
The ISL9203A can work with a current-limited adapter to
significantly reduce the thermal dissipation during charging.
Refer to the ISL6292 data sheet, which can be found at
http://www.intersil.com, for more details.
Board Layout Recommendations
The ISL9203A internal thermal foldback function limits the
charge current when the internal temperature reaches
approximately +100°C. In order to maximize the current
capability, it is very important that the exposed pad under the
package is properly soldered to the board and is connected
to other layers through thermal vias. More thermal vias and
more copper attached to the exposed pad usually result in
better thermal performance. On the other hand, the number
of vias is limited by the size of the pad. The 3x3 DFN
package allows 8 vias be placed in two rows. Since the pins
on the 3x3 DFN package are on only two sides, as much top
layer copper as possible should be connected to the
exposed pad to minimize the thermal impedance. Refer to
the ISL6292 evaluation boards for layout examples.
FIGURE 23. PULL-UP CIRCUIT TO AVOID BATTERY
LEAKAGE CURRENT IN THE ESD DIODES
STATUS
VIN
ESD DIODE
C
EN
VCC
GND
VIN or
V2P8
R1
Note:
R
is approximately 240k
Ω
when EN is floating and
is approximately 140k
Ω
when the EN is grounded.
R
LKG
Q1
ISL9203A
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