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參數(shù)資料
| 型號： | ISL90842UIV1427Z-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DGTL QUAD 50K OHM 14TSSOP |
| 產(chǎn)品培訓模塊： | Digitally Controlled Potentiometers |
| 標準包裝： | 1 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±45 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1237 (CN2011-ZH PDF) |
| 其它名稱： | ISL90842UIV1427Z-TKDKR |
9
FN8096.1
January 16, 2006
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90842 responds with an ACK. At this time, the device
enters its standby state (See Figure 11).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 12). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90842 responds with an ACK. Then the ISL90842
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 12).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
FIGURE 12. READ SEQUENCE
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
A
C
K
A
C
K
00
0
11
S
T
O
P
A
C
K
IDENTIFICATION
BYTE WITH
R/W=1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
0
00 0
0 0
0 A1A0
01
0
11 0 A1A0
ISL90842
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| VE-B2X-MY-F1 | CONVERTER MOD DC/DC 5.2V 50W |
| VE-B2W-MY-F4 | CONVERTER MOD DC/DC 5.5V 50W |
| ISL90842WIV1427Z-TK | IC POT DGTL QUAD 10K OHM 14TSSOP |
| VE-B2W-MY-F2 | CONVERTER MOD DC/DC 5.5V 50W |
| VE-B2W-MY-F1 | CONVERTER MOD DC/DC 5.5V 50W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL90842WIV1427 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise, Low Power, I2C Bus, 256 Taps |
| ISL90842WIV1427Z | 功能描述:IC DCP 256-TAP 10KOHM TSSOP-14 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) |
| ISL90842WIV1427Z-TK | 功能描述:IC POT DGTL QUAD 10K OHM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應商設備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| ISL90843 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers (XDCP⑩) |
| ISL90843UIU1027Z | 功能描述:IC XDCP 256-TAP 50OHM MSOP-10 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:32 電阻（歐姆）:50k 電路數(shù):1 溫度系數(shù):標準值 50 ppm/°C 存儲器類型:易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 細型，TSOT-23-6 供應商設備封裝:TSOT-23-6 包裝:帶卷 (TR) |
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