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參數(shù)資料
| 型號： | ISL90842 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power, I2C Bus, 256 Taps |
| 中文描述： | 低噪聲，低功耗，I2C總線，256絲錐 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 1165K |
| 代理商： | ISL90842 |
9
FN8096.0
June 14, 2005
Principles of Operation
The ISL90842 is an integrated circuit incorporating four
DCPs with their associated registers, and an I
2
C serial
interface providing direct communication between a host
and the potentiometers.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer. The RW pin of each DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by an 8-bit volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper
terminal (RW) is closest to its RL terminal. When the WR of a
DCP contains all ones (WR<7:0>: FFh), its wiper terminal
(RW) is closest to its RH terminal. As the value of the WR
increases from all zeroes (00h) to all ones (255 decimal), the
wiper moves monotonically from the position closest to RL to
the closest to RH. At the same time, the resistance between
RW and RL increases monotonically, while the resistance
between RH and RW decreases monotonically.Note that the
RL terminal for all 4 pots are not connected (left floating).
While the ISL90842 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at the
center between RL and RH.
The WRs can be read or written directly using the I
2
C serial
interface as described in the following sections. The I
2
C
interface Address Byte has to be set to 00hex, 01hex,
02hex, and 03hex to access the WR of DCP0, DCP1, DCP2,
and DCP3 respectively
I
2
C Serial Interface
The ISL90842 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90842
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL90842 the SDA pin is in
the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90842 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the power-
up of the device.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15). A STOP condition at the end
of a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The ISL90842 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90842 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 0101 as the four MSBs,
then a 0, the two bits matching the logic values present at
pins A1 and A0. The LSB is in the Read/Write bit. Its value is
“1” for a Read operation, and “0” for a Write operation (See
Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
Logic values at pins A1, and A0 respectively
0
1
0
1
0
A1
A0
R/W
(MSB)
(LSB)
ISL90842
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| ISL90842UIV1427Z | 功能描述:IC DCP 256-TAP 50KOHM TSSOP-14 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| ISL90842UIV1427Z-TK | 功能描述:IC POT DGTL QUAD 50K OHM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| ISL90842WIV1427 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise, Low Power, I2C Bus, 256 Taps |
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