I
參數(shù)資料
型號(hào)： ISL90728WIE627Z-TK
廠商： Intersil
文件頁數(shù)： 4/8頁
文件大?。?/td> 0K
描述： IC XDCP 128-TAP 10OHM SC70-6
標(biāo)準(zhǔn)包裝： 1
系列： XDCP™
接片： 128
電阻（歐姆）： 10k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±45 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝： SC-70-6
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1237 (CN2011-ZH PDF)
其它名稱： ISL90728WIE627Z-TKDKR
4
FN8247.8
May 10, 2012
Operating Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 19)
TYP
(Note 7)
MAX
(Note 19) UNIT
ICC1
VCC Supply Current
(Volatile write/read)
fSCL = 400kHz; SDA = Open; (for I
2C, Active,
Read and Volatile Write States only)
200
A
ISB
VCC Current (standby)
VCC = +5.5V, I
2C Interface in Standby State
500
nA
IComLkg
Common-Mode Leakage
Voltage at SDA pin to GND or VCC
3A
tDCP (Note 16) DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
500
ns
VCCRamp
(Note 20)
VCC Ramp Rate
0.2
V/ms
tD
Power-up Delay
VCC above VPOR, to DCP Initial Value Register
recall completed, and I2C Interface in standby state
3ms
SERIAL INTERFACE SPECIFICATIONS
VIL
SDA, and SCL Input Buffer LOW
Voltage
(Note 17)
-0.3
0.3*
VCC
V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
(Note 17)
0.7*
VCC
VCC+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
VCC
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin (Note 18) SDA and SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window.
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC window.
0ns
tR (Note 18)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1*Cb
250
ns
ISL90727, ISL90728
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