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參數(shù)資料
| 型號： | ISL90726 |
| 廠商： | Intersil Corporation |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Digitally Controlled Potentiometer (XDCP) |
| 中文描述： | 數(shù)控電位器（數(shù)字電位器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 226K |
| 代理商： | ISL90726 |
5
FN8244.1
August 3, 2005
SDA vs SCL Timing
NOTES:
1. Typical values are for T
A
= 25°C and 3.3V supply voltage.
2. LSB: [V(R
W
)
127
– V(R
W
)
0
]
/
127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = V(R
W
)
0
/
LSB.
4. FS error = [V(R
W
)
127
– V
CC
]
/
LSB.
5. MI =
|
R
127
– R
0
|
/
127. R
127
and R
0
are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
Roffset = R
0
/
MI, when measuring between R
W
and R
L
.
6. Roffset = R
127
/
MI, when measuring between R
W
and R
H
.
7. RDNL = (R
i
– R
i-1
)
/
MI, for i = 32 to 127.
8. RINL = [R
i
– (MI i) – R
0
]
/
MI, for i = 32 to 127.
6
125°C
9.
for i = 32 to 127, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the
minimum value of the resistance over the temperature range.
10. This parameter is not 100% tested.
11. V
IL
= 0V, V
IH
= V
CC.
12. These are I
2
C-specific parameters and are not directly tested. However, they are used in the device testing to validate specifications.
Principles of Operation
The ISL90726 is an integrated circuit incorporating one DCP
with its associated registers and an I
2
C serial interface
providing direct communication between a host and the
potentiometer.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
pins). The R
W
pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 7-bit
volatile Wiper Register (WR). The DCP has its own WR.
When the WR of the DCP contains all zeroes (WR<6:0>=
00h), its wiper terminal (R
W
) is closest to its “Low” terminal
(R
L
). When the WR of the DCP contains all ones
(WR<6:0>=7Fh), its wiper terminal (R
W
) is closest to its
“High” terminal (R
H
). As the value of the WR increases from
all zeroes (00h) to all ones (127 decimal), the wiper moves
monotonically from the position closest to R
L
to the position
closest to R
H
. R
H
is not connected to a device pin. The net
effect is the resistance between R
W
and R
L
increases
monotonically.
While the ISL90726 is being powered up, the WR is reset to
20h (64 decimal), which locates R
W
roughly at the center
between R
L
and R
H
.
The WR and IVR can be read or written directly using the
I
2
C serial interface as described in the following sections.
I
2
C Serial Interface
The ISL90726 supports bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90726
operates as slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
TC
R
Max Ri
+
Min Ri
]
)
)
[
]
2
------------------------------–
----------------
×
=
ISL90726
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