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參數資料
| 型號： | ISL88731 |
| 廠商： | Intersil Corporation |
| 英文描述： | SMBus Level 2 Battery Charger |
| 中文描述： | 2級的SMBus電池充電器 |
| 文件頁數： | 19/22頁 |
| 文件大小： | 474K |
| 代理商： | ISL88731 |
19
FN9258.0
November 20, 2006
The loop response equations, bode plots and the selection
of C
ICOMP
are the same as the charge current control loop
with loop gain reduced by the duty cycle and the ratio of
R
S1
/R
S2
. In other words, if R
S1
= R
S2
and the duty cycle
D = 50%, the loop gain will be 6dB lower than the loop gain
in Figure 22. This gives lower crossover frequency and
higher phase margin in this mode. If R
S1
/R
S2
= 2 and the
duty cycle is 50% then the adapter current loop gain will be
identical to the gain in Figure 22.
A filter should be added between R
S1
and CSIP and CSIN to
reduce switching noise. The filter roll off frequency should be
between the cross over frequency and the switching
frequency (~100kHz).
Voltage Control Loop
When the battery is charged to the voltage set by
ChargeVoltage register the voltage error amplifier (GMV)
takes control of the output (assuming that the adapter
current is below the limit set by ACLIM). The voltage error
amplifier (GMV) discharges the cap on VCOMP to limit the
output voltage. The current to the battery decreases as the
cells charge to the fixed voltage and the voltage across the
internal battery resistance decreases. As battery current
decreases the 2 current error amplifiers (GMI and GMS)
output their maximum current and charge the capacitor on
ICOMP to its maximum voltage (limited to 0.3V above
VCOMP). With high voltage on ICOMP, the minimum voltage
buffer output equals the voltage on VCOMP.
The voltage control loop is shown in Figure 23.
Output LC Filter Transfer Functions
The gain from the phase node to the system output and
battery depend entirely on external components. Typical
output LC filter response is shown in Figure 24. Transfer
function A
LC
(s) is shown in Equation 22:
2
DP
The resistance R
O
is a combination of MOSFET r
DS(ON)
,
inductor DCR, R
SENSE
and the internal resistance of the
battery (normally between 50m
Ω
and 200m
Ω
) The worst
case for voltage mode control is when the battery is absent.
This results in the highest Q of the LC filter and the lowest
phase margin.
The compensation network consists of the voltage error
amplifier GMV and the compensation network R
VCOMP
,
C
VCOMP
which give the loop very high DC gain, a very low
frequency pole and a zero at F
ZERO1
. Inductor current
-60
-40
-20
0
20
40
60
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
G
Compensator
Modulator
Loop
F
F
ZERO
POLE1
F
FILTER
F
POLE2
FIGURE 21. CHARGE CURRENT LOOP BODE PLOTS
C
ICOMP
R
BAT
ICOMP
PHASE
11
S
Σ
+
-
0.25
DACS
+
-
GMS
R
S1
DCIN
CSSN
+
-
CA1
20
CSSP
C
F1
R
F1
R
S2
CSON
+
-
20X
CSOP
C
F2
R
F2
R
ESR
C
O
L
R
FET_RDSON
R
L_DCR
CA2
FIGURE 22. ADAPTER CURRENT LIMIT LOOP
FIGURE 23. VOLTAGE CONTROL LOOP
VCOMP
CSON
PHASE
11
CSOP
S
Σ
+
-
0.25
+
-
GMV
C
VCOMP
R
VCOMP
DACV
R3
R4
+
-
20X
R
S2
R
BAT
R
ESR
C
O
C
F2
R
F2
L
R
FET_RDSON
R
L_DCR
CA2
A
LC
1
---------------
–
-----------
LC
)
------------------------
1
+
+
----------------------------------------------------------
=
ω
ESR
ESR
o
)
--------------------------------
=
ω
LC
L C
o
(
)
-----------------------
=
Q
R
o
L
C
o
------
=
(EQ. 22)
ISL88731
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