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參數(shù)資料
| 型號： | ISL8560 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | DC/DC Power Switching Regulator |
| 中文描述： | DC/DC電源開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 1016K |
| 代理商： | ISL8560 |
15
FN9244.6
September 18, 2007
Compensation Break Frequency
Equations
g
m
π
R
2
C
7
Assumption: R6<<R2, R6<<R3, and C10<<C6.
Figure 31 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 31. Using the guidelines on
page 14 should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at f
P2
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the graph of Figure 31 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, titled
“Designing Stable Compensation Networks for Single Phase
Voltage Mode Buck Regulators.”
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently
between 100kHz and 600kHz, the resulting current
transitions from one device to another cause voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device overvoltage
stress. Careful component layout and printed circuit board
design minimizes these voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the freewheeling Schottky
diode. Any parasitic inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in the ISL8560
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
f
Z1
2
π
1
+
---------------------------------
C
6
)
--------------R
=
f
Z2
2
=
f
P1
π
R
6
C
7
2
=
f
P2
π
R
4
C
10
2
=
(EQ. 12)
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100k
10k
1k
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
4
/R
2
)
F
LC
F
ESR
COMPENSATION
GAIN
CLOSED LOOP
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
Δ
V
OSC
)
MODULATOR
GAIN
FIGURE 31. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
VIN
ISL8560
VCC5
LX
PGND
COMP
FB
GND PAD
R
3
R
6
C
7
R
2
C
10
C
6
R
4
C
OUT1
V
OUT1
C
IN
V
IN
L
C
BP2
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
KEY
L
FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
D
ISL8560
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