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參數(shù)資料
| 型號： | ISL8500 |
| 廠商： | Intersil Corporation |
| 英文描述： | Switching Regulator Control (Voltage Mode type AC/DC) ; Vin (V) max.: 10 to 35; Icc (mA) max.: 15; Fmax (kHz) max.: 500; Topr [Tjopr] (°C): -30 to +85; Remarks: Primary control MOSFET drive; Package: SOP; Pin count: 20 |
| 中文描述： | 甲標(biāo)準(zhǔn)降壓PWM穩(wěn)壓器 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 622K |
| 代理商： | ISL8500 |
13
FN6611.0
December 10, 2007
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 21 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The error
amplifier output (V
E/A
) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
IN
at the PHASE node. The
PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
Δ
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL8500) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180°. Equation 8 relates the compensation network’s poles,
zeros and gain to the components (R
1
, R
2
, R
3
, C
1
, C
2
, and
C
3
) in Figure 22. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 22 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 22. Using the previously
mentioned guidelines should give a Compensation Gain
similar to the curve plotted. The open loop error amplifier
gain bounds the compensation gain. Check the
compensation gain at F
P2
with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph
of Figure 4 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
V
DDQ
REFERENCE
L
O
C
O
ESR
V
IN
Δ
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
OUT
FB
Z
FB
ISL8500
Z
IN
COMPARATOR
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
R
4
D
FLC
2
π
x LO x CO
--------------------1
=
FESR
π
x ESR x CO
2
=
(EQ. 7)
F
Z1
π
x R
2
x C
2
2
=
F
Z2
+
π
x R
1
R
3
(
)
x C
3
2
=
F
P1
2
π
x R
2
x
C
x C
2
1
C
2
+
C
---------------------------1
=
F
P2
π
x R
3
x C
3
2
=
(EQ. 8)
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100k
10k
1k
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
2
/R
1
)
F
LC
F
ESR
COMPENSATION
GAIN
CLOSED LOOP
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
Δ
V
OSC
)
MODULATOR
GAIN
FIGURE 22. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
ISL8500
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