參數(shù)資料
型號(hào)： ISL6753AAZA-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： ZVS Full-Bridge PWM Controller
中文描述： 0.1 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16
封裝： 0.150 INCH, ROHS COMPLIANT, PLASTIC, QSOP-16
文件頁(yè)數(shù)： 12/15頁(yè)
文件大?。?/td> 465K
代理商： ISL6753AAZA-T
12
FN9182.1
March 10, 2005
R6 = 499
Solve for the current sense resistor, R
CS
, using EQ. 18.
R
CS
= 15.1
.
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using EQ. 15.
Ve = 153mV
Next, determine the effect of the magnetizing current from
EQ. 20.
V
CS
= 91mV
Using EQ. 23, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1k
Determine the new value of R
CS
, R’
CS
, using EQ. 24.
R’
CS
= 15.4
The above discussion determines the minimum external
ramp that is required. Additional slope compensation may be
considered for design margin.
f the application requires deadtime less than about 500nS,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400nS. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that EQs. 21 and 22
require modification. EQ. 21 becomes:
and EQ. 22 becomes:
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain so as to minimize the
required base current. Whatever base current is required
reduces the charging current into CT and will reduce the
oscillator frequency.
ZVS Full-Bridge Operation
The ISL6753 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
FIGURE 8. ADDING SLOPE COMPENSATION USING CT
R6
C4
R9
R
CS
CT
CT
CS
1
2
4
3
5
6
7
8
9
10
11
12
13
14
15
16
ISL6753
VREF
V
e
V
CS
–
R9
--------+
=
V
(EQ. 25)
R9
2D
-----------------------–
V
e
V
CS
+
–
(
)
R6
=
(EQ. 26)
FIGURE 9. BRIDGE DRIVE SIGNAL TIMING
CT
DEADTIME
OUTLL
OUTLR
OUTUR
OUTUL
RESDEL
WINDOW
RESONANT
DELAY
PWM
PWM
PWM
PWM
ISL6753
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