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參數(shù)資料
| 型號： | ISL6722AAVZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Flexible Single Ended Current Mode PWM Controllers |
| 中文描述： | 1 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-153AB, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 13/23頁 |
| 文件大小： | 428K |
| 代理商： | ISL6722AAVZ |
13
FN9237.0
October 19, 2005
Figure 6 depicts overcurrent behavior during soft-start.
ISENSE’ represents the scaled values of ISENSE at the
input to the overcurrent comparator.
Although an overcurrent condition exists, a shutdown is not
allowed prior to completion of the SS cycle. Only peak
current limit operates during the soft-start cycle. If the
overcurrent condition were to continue beyond the soft-start
cycle, a delayed overcurrent shutdown would occur as
shown in Figure 7, below.
If the overcurrent condition is removed prior to a shutdown, a
recovery can occur as indicated in Figure 8. When the load
decreases below the overcurrent threshold and an additional
50μs elapses without the SS dropping below 4.375V, the
overcurrent circuitry resets and the soft-start voltage
recovers.
Leading Edge Blanking
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry.
The blanking period begins when the GATE output leading
edge exceeds 3.0V. Leading edge blanking prevents current
spikes from parasitic elements in the power supply from
causing false trips of the PWM comparator and the
overcurrent comparator.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV
input exceeds 2.50V, or the UV input falls below 1.45V.
When a Fault is detected, the GATE output is disabled and
the soft-start capacitor is quickly discharged. When the Fault
condition clears and the soft-start voltage is below the reset
threshold, a soft-start cycle begins.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the logic ground (LGND) and
connected at a single point. V
C
should be bypassed directly
to PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor
should be connected to the PGND ground plane.
Reference Design
The Typical Application Schematic features the ISL6722A in
a conventional dual output 10W discontinuous mode flyback
DC/DC converter. The ISL6722AEVAL1 demonstration unit
implements this design and is available for evaluation.
The input voltage range is from 36 to 75V DC, and the two
outputs are 3.3V @ 2.5A and 1.8V @ 1.0A. Cross regulation
is achieved using the weighted sum of the two outputs.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
Input Storage and Filtering Capacitance: C1, C2, C3
Isolation Transformer: T1
Primary voltage Clamp: CR6, R24, C18
Start Bias Regulator: R1, R2, R6, Q3, VR1
Operating Bias and Regulator: R25, Q2, D1, C5, CR2, D2
Main MOSFET Power Switch: Q1
Current Sense Network: R4, R3, R23, C4
Feedback Network:, R13, R15, R16, R17, R18, R19, R20,
R26, R27, C13, C14, U2, U3
Control Circuit: C7, C8, C9, C10, C11, C12, R5, R6, R8, R9,
R10, R11, R12, R14, R22
Output Rectification and Filtering: CR4, CR5, C15, C16,
C19, C20, C21, C22
Secondary Snubber: R21, C17
FIGURE 6. PULSE-BY-PULSE OC BEHAVIOR DURING SS
SS
ISET
ISENSE
GATE
4.5 V
FIGURE 7. OC SHUTDOWN BEHAVIOR
SS
ISENSE'
GATE
4.5 V
4.375 V
GND
ISET
295ms
FIGURE 8. OC RECOVERY PRIOR TO SHUTDOWN
SS
ISENSE'
GATE
4.5 V
4.375 V
ISET
50
μ
S
OC
ISL6722A, ISL6723A
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