參數(shù)資料
型號: ISL6722A
廠商: Intersil Corporation
元件分類: DRAM
英文描述: 1024 x 9 x 2 Asynchronous Bidirectional FIFO Memory 44-PLCC 0 to 70
中文描述: 靈活的單端電流模式PWM控制器
文件頁數(shù): 20/23頁
文件大?。?/td> 428K
代理商: ISL6722A
20
FN9237.0
October 19, 2005
Waveforms
Typical waveforms can be found in Figures 13 through 15.
These waveforms are taken from an ISL6721EVAL1
evaluation board, and therefore include synchronization
waveforms that are not applicable to the ISL6722A, but are
otherwise representative. Figure 13 shows the steady state
operation of the sawtooth oscillator waveform at RTCT
(Trace 2), the SYNC output pulse (Trace 1), and the GATE
output to the converter FET (Trace 3). Figure 14 shows the
converter behavior while operating in an overcurrent fault
condition. Trace 1 is the soft-start voltage, which increases
from zero to 4.5V, at which point the OC fault function is
enabled. The OC condition is detected and the soft-start
capacitor is discharged to the 4.375V OC fault threshold at
which point the IC enters the fault shutdown mode. Trace 2
shows the behavior of the timing capacitor voltage during a
shutdown fault. Most of the functions of the IC are de-
powered during a fault, and the oscillator is among those
functions. During a fault, the IC is turned off until the restart
delay has timed out. After the delay, power is restored and
the IC resumes normal operation. Trace 3 is the GATE
output during the soft-start cycle and OC fault.
Figure 15 shows the switching FET waveforms during
steady state operation. Trace 1 is drain - source voltage and
Trace 2 is gate - source voltage.
FIGURE 13. TYPICAL WAVEFORMS
NOTE:
Trace 1: SYNC Output
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
FIGURE 14. SOFT-START WITH OVERCURRENT FAULT
NOTE:
Trace 1: SS
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
FIGURE 15. GATE AND DRAIN-SOURCE WAVEFORMS
NOTE:
Trace 1: V
D-S
Trace 3: V
G-S
ISL6722A, ISL6723A
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