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參數(shù)資料
| 型號(hào)： | ISL6722A |
| 廠商： | Intersil Corporation |
| 元件分類： | DRAM |
| 英文描述： | 1024 x 9 x 2 Asynchronous Bidirectional FIFO Memory 44-PLCC 0 to 70 |
| 中文描述： | 靈活的單端電流模式PWM控制器 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 428K |
| 代理商： | ISL6722A |
16
FN9237.0
October 19, 2005
The conduction losses are due to the MOSFET’s ON
resistance.
where r
DS(ON)
is the ON resistance of the MOSFET and
Iprms is the RMS primary current. Determining the
conduction losses is complicated by the variation of r
DS(ON)
with temperature. As junction temperature increases, so
does r
DS(ON)
, which increases losses and raises the
junction temperature more, and so on. It is possible for the
device to enter a thermal runaway situation without proper
heatsinking. As a general rule of thumb, doubling the 25°C
r
DS(ON)
specification yields a reasonable value for
estimating the conduction losses at 125°C junction
temperature.
The switching losses have two components, capacitive
switching losses and voltage/current overlap losses. The
capacitive losses occur during turn on of the device and may
be calculated as follows:
where Cfet is the equivalent output capacitance of the
MOSFET. Device output capacitance is specified on
datasheets as Coss and is non-linear with applied voltage.
To find the equivalent discrete capacitance, Cfet, a charge
model is used. Using a known current source, the time
required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance may be calculated.
The other component of the switching loss is due to the
overlap of voltage and current during the switching
transition. A switching transition occurs when the MOSFET
is in the process of either turning on or off. Since the load is
inductive, there is no overlap of voltage and current during
the turn on transition, so only the turn off transition is of
significance. The power dissipation may be estimated as:
where Tol is the duration of the overlap period and x ranges
from about 3 - 6 in typical applications and depends on
where the waveforms intersect. This estimate may predict
higher dissipation than is realized because a portion of the
turn off drain current is attributable to the charging of the
device output capacitance (Coss) and is not dissipative
during this portion of the switching cycle.
The final component of MOSFET loss is caused by the
charging of the gate capacitance through the device gate
resistance. Depending on the relative value of any external
resistance in the gate drive circuit, a portion of this power will
be dissipated externally.
Once the losses are known, the device package must be
selected and the heatsinking method designed. Since the
design requires a small surface mount part, a SOIC-8
package was selected. A Fairchild FDS2570 MOSFET was
selected based on these criteria. The overall losses are
estimated at 400mW.
Output Filter Design
In a flyback design, the primary concern for the design of the
output filter is the capacitor ripple current stress and the
ripple and noise specification of the output.
The current flowing in and out of the output capacitors is the
difference between the winding current and the output
current. The peak secondary current, Ispk, is 10.73A for the
3.3V output and 4.29A for the 1.8V output. The current
flowing into the output filter capacitor is the difference
between the winding current and the output current. Looking
at the 3.3V output, the peak winding current is Ispk =
10.73A. The capacitor must store this amount minus the
output current of 2.5A, or 8.23A. The RMS ripple current in
the 3.3V output capacitor is about 3.5Arms. The RMS ripple
current in the 1.8V output capacitor is about 1.4Arms
Voltage deviation on the output during the switching cycle
(ripple and noise) is caused by the change in charge of the
output capacitance, the equivalent series resistance (ESR),
and equivalent series inductance (ESL). Each of these
components must be assigned a portion of the total ripple
and noise specification. How much to allow for each
contributor is dependent on the capacitor technology used.
Pcond
r
DS ON
)
Iprms
2
=
W
Pswcap
1
2
--
Cfet
Vin
2
Fsw
=
W
(EQ. 31)
Cfet
-------------------
t
=
F
(EQ. 32)
Psw
1
x
--
Ippk
Vin
Tol
Fsw
≈
(EQ. 33)
V
D-S
Ippk
Tol
FIGURE 9.
Pgate
Qg
Vg
Fsw
=
W
(EQ. 34)
ISL6722A, ISL6723A
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