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參數(shù)資料
| 型號： | ISL6551ABZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 500-mA Peak Step-Up, Step-Down, Inverting Switching Voltage Regulator 14-PDIP -40 to 85 |
| 中文描述： | DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-013AE, SOIC-28 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 619K |
| 代理商： | ISL6551ABZ |
8
FN9066.4
July 8, 2005
Drive Signals Timing Diagrams
Timing Diagram Descriptions
The two upper drivers (UPPER1 and UPPER2) are driven at
a fixed 50% duty cycle and the two lower drivers (LOWER1
and LOWER2) are PWM-controlled on the trailing edge,
while the leading edge employs resonant delay (T2 and T4).
In current mode control, the sensed switch (FET) current
(I
LOWER1
and I
LOWER2
) is processed in the Ramp Adjust
and Leading Edge Blanking (LEB) circuits and then compared
to a control signal (EAO). Spikes, due to parasitic elements in
the bridge circuit, would falsely trigger the comparator
generating the PWM signal. To prevent false triggering, the
leading edge of the sensed current signal is blanked out by
T1, which can be programmed at the R_LEB pin with a
resistor. Internal switches gate the analog input to the PWM
comparator, implementing the blanking function that
eliminates response degrading delays which would be caused
if filtering of the current feedback was incorporated. The dead
time (T3 and T5) is the delay to turn on the upper FET
(UPPER1/UPPER2) after its corresponding lower FET
(LOWER1/LOWER2) is turned off when the bridge is
operating at maximum duty cycle in normal conditions, or is
responding to load transients or input line dipping conditions.
Therefore, the upper and lower FETs that are located at the
same side of the bridge can never be turned on together, which
eliminates shoot-through currents. SYNC1 and SYNC2 are the
gate control signals for the output synchronous rectifiers. They
are biased by VDD and are capable of driving capacitive loads
up to 20pF at 1MHz clock frequency (500kHz switching
frequency). External drivers with high current capabilities are
required to drive the synchronous rectifiers, cascading with
both synchronous signals (SYNC1 and SYNC2).
CLOCK
UPPER1
UPPER2
SYNC1
SYNC2
LOWER1
I
LOWER1
RAMP ADJUST
OUTPUT TO
PWM
LOGIC
T1
T2
T3
T4
T5
T1 = Leading edge blanking
T2 = T4 = Resonant delay
T3 = T5 = dead time
In the above figure, the values for T1 through T5 are exaggerated for demonstration purposes.
LOWER2
NOTES:
EAO
I
LOWER2
EAO
EAO
ISL6551
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