參數(shù)資料
型號(hào): ISL6537CR
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: ACPI Regulator/Controller for Dual Channel DDR Memory Systems
中文描述: 3.3 A SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC28
封裝: 6 X 6 MM, PLASTIC, MO-220-VJJC, QFN-28
文件頁(yè)數(shù): 12/15頁(yè)
文件大?。?/td> 560K
代理商: ISL6537CR
12
FN9142.4
February 8, 2005
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6537) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 4 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 4 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 3.
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
V
DDQ
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
DDQ
FB
Z
FB
ISL6537
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
R
4
V
DDQ
0.8
1
R
1
R
4
------
+
×
=
FLC
2
π
x
LO
x
CO
------------------------------------------
=
FESR
x
ESR
x
CO
-------------------------------------------
=
F
Z1
π
x R
2
x C
1
2
=
F
Z2
+
π
x R
1
R
3
)
x C
3
2
=
F
P1
2
π
x R
2
x
C
x C
2
1
+
C
2
C
---------------------------1
=
F
P2
π
x R
3
x C
3
2
=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
2
/R
1
)
F
LC
F
ESR
COMPENSATION
GAIN
CLOSED LOOP
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
V
OSC
)
MODULATOR
GAIN
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
ISL6537
相關(guān)PDF資料
PDF描述
ISL6537CRZ 500-mA Peak Step-Up, Step-Down, Inverting Switching Voltage Regulator 14-SOIC 0 to 70
ISL6537CRZ-T 500-mA Peak Step-Up, Step-Down, Inverting Switching Voltage Regulator 14-SOIC 0 to 70
ISL6539 Wide Input Range Dual PWM Controller with DDR Option
ISL6539CA Wide Input Range Dual PWM Controller with DDR Option
ISL6539CA-T Wide Input Range Dual PWM Controller with DDR Option
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL6537CR-T 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像,聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-TQFN-EP(8x8) 包裝:管件
ISL6537CRZ 功能描述:IC REG/CTLR ACPI DUAL DDR 28QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 應(yīng)用:熱電冷卻器 電流 - 電源:- 電源電壓:3 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC(0.173",4.40mm 寬)裸露焊盤 供應(yīng)商設(shè)備封裝:28-TSSOP 裸露焊盤 包裝:管件 產(chǎn)品目錄頁(yè)面:1410 (CN2011-ZH PDF)
ISL6537CRZA-TR5160 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像,聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-TQFN-EP(8x8) 包裝:管件
ISL6537CRZR5160 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像,聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-TQFN-EP(8x8) 包裝:管件
ISL6537CRZ-T 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:37 系列:- 應(yīng)用:醫(yī)療用超聲波成像,聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-TQFN-EP(8x8) 包裝:管件