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參數(shù)資料
| 型號(hào)： | ISL6532CR-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | PWM Control Circuit 16-PDIP 0 to 70 |
| 中文描述： | SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | 6 X 6 MM, PLASTIC, MO-220VJJB, QFN-20 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大小： | 365K |
| 代理商： | ISL6532CR-T |
6
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6532. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532 enters a reduced
power mode and draws less than 1mA (I
CC5
) from the
5VSBY supply. This pin should be locally bypassed using a
0.1
μ
F capacitor.
P12V (Pin 18)
P12V provides the gate drive current to the switching
MOSFETs of the PWM power stage. The V
TT
regulation
circuit is also powered by P12V. P12V is only required during
S0/S1/S2 operation. P12V is typically connected to the +12V
rail of an ATX power supply.
P5VSBY (Pin 8)
This pin provides the V
DDQ
output power during the S3
sleep state. The regulator is capable of providing standby
V
DDQ
power from either a 5V or 3.3V source.
GND (Pin 2, 13, 21)
The GND terminals of the ISL6532 provide the return path
for the V
TT
LDO, Standby LDO and switching MOSFET gate
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible.
UGATE (Pin 20)
UGATE drives the upper (control) FET of the V
DDQ
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
LGATE (Pin 19)
LGATE drives the lower (synchronous) FET of the V
DDQ
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
I
GATE
-
-0.8
-
A
UGATE and LGATE Sink
I
GATE
-
0.8
-
A
NCH BACKFEED CONTROL
NCH Current Sink
I
NCH
NCH = 0.8V
-
-
6
mA
NCH Trip Level
V
NCH
9.0
9.5
10
V
VDDQ STANDBY LDO
Output Drive Current
P5VSBY = 5.0V
-
-
650
mA
P5VSBY = 3.3V
-
-
550
mA
VTT REGULATOR
Upper Divider Impedance
R
U
-
2.5
-
k
Lower Divider Impedance
R
L
-
2.5
-
k
VREF_OUT Buffer Source Current
I
VREF_OUT
-
-
2
mA
Maximum V
TT
Load Current
I
VTT_MAX
Periodic load applied with 30% duty cycle
and 10ms period using ISL6532EVAL1
evaluation board (see Application Note
AN1055)
-3
-
3
A
PGOOD
PGOOD Rising Threshold
V
VTTSNS/
V
VDDQ
S3# & S5# HIGH
-
57.5
-
%
PGOOD Falling Threshold
V
VTTSNS/
V
VDDQ
S3# & S5# HIGH
-
45.0
-
%
PROTECTION
VDDQ OV Level
V
FB
/V
REF
S3# & S5# HIGH
-
115
-
%
VDDQ UV Level
V
FB
/V
REF
S3# & S5# HIGH
-
85
-
%
Thermal Shutdown Limit
T
SD
By Design
-
140
-
°C
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6532
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