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參數(shù)資料
| 型號： | ISL6532ACR |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | ACPI Regulator/Controller for Dual Channel DDR Memory Systems |
| 中文描述： | 3 A SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 6 X 6 MM, PLASTIC, MO-220VJJC, QFN-28 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 504K |
| 代理商： | ISL6532ACR |
8
The calculated capacitance, C
SS
, will charge the output
capacitor bank on the V
TT
rail in a controlled manner without
reaching the current limit of the V
TT
LDO.
NCH (Pin 22)
NCH is an open-drain output that controls the MOSFET
blocking backfeed from V
DDQ
to the input rail during sleep
states. A 2k
or larger resistor is to be tied between the 12V
rail and the NCH pin. Until the voltage on the NCH pin
reaches the NCH trip level, the PWM is disabled.
If NCH is not actively utilized, it still must be tied to the 12V
rail through a resistor. For systems using 5V dual as the
input to the switching regulator, a time constant, in the form
of a capacitor, can be added to the NCH pad to delay start of
the PWM switcher until the 5V dual has switched from
5VSBY to 5VATX.
PGOOD (Pin 21)
Power Good is an open-drain logic output that changes to a
logic low if any of the three regulators are out of regulation in
S0/S1/S2 state. PGOOD will always be low in any state other
than S0/S1/S2.
SLP_S5# (Pin 24)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 23)
This pin accepts the SLP_S3# sleep state signal.
FB2 (Pin 18)
Connect the output of the external linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V. This pin is monitored for under and
over-voltage events.
DRIVE2 (Pin 19)
Connect this pin to the gate terminal of an external N-
Channel MOSFET transistor. This pin provides the gate
voltage for the linear regulator pass transistor. It also
provides a means of compensating the error amplifier for
applications requiring the transient response of the linear
regulator to be optimized.
Functional Description
Overview
The ISL6532A provides complete control, drive, protection
and ACPI compliance for a regulator powering DDR memory
systems. It is primarily designed for computer applications
powered from an ATX power supply. A 250kHz Synchronous
Buck Regulator with a precision 0.8V reference provides the
proper Core voltage to the system memory of the computer.
An internal LDO regulator with the ability to both sink and
source current and an externally available buffered reference
that tracks the V
DDQ
output by 50% provides the V
TT
termination voltage. The ISL6532A also features an LDO
regulator for 1.5V AGP Video and Core voltage.
ACPI compliance is realized through the SLP_S3 and
SLP_S5 sleep signals and through monitoring of the 12V
ATX bus.
Initialization
The ISL6532A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors
the bias voltage at the 5VSBY and P12V pins. The POR
function initiates soft-start operation after the bias supply
voltages exceed their POR thresholds.
ACPI State Transitions
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, the ISL6532A receives it’s
bias voltage from the 5V Standby bus (5VSBY). As soon as
the SLP_S3 and SLP_S5 have transitioned HIGH, the
ISL6532A starts an internal counter. Following a cold start or
any subsequent S4/S5 state, state transitions are ignored
until the system enters S0/S1. None of the regulators will
begin the soft start procedure until the 5V Standby bus has
exceeded POR, the 12V bus has exceeded POR and V
NCH
has exceeded the trip level.
Once all of these conditions are met, the PWM error
amplifier will first be reset by internally shorting the COMP
pin to the FB pin. This reset lasts for 2048 clock cycles,
which is typically 8.2ms (one clock cycle = 1/f
OSC
). The
digital soft start sequence will then begin.
The PWM error amplifier reference input is clamped to a
level proportional to the soft-start voltage. As the soft-start
voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output
capacitor(s). The internal VTT LDO will also soft start
through the reference that tracks the output of the PWM
regulator. The reference for the AGP LDO controller will rise
relative to the soft start reference. The soft start lasts for
2048 clock cycles, which is typically 8.2ms. This method
provides a rapid and controlled output voltage rise.
Figure 1 shows the soft start sequence for a typical cold
start. Due to the soft start capacitance, C
SS
, on the
VREF_IN pin, the S5 to S0 transition profile of the V
TT
rail
will have a more rounded features at the start and end of the
soft start whereas the V
DDQ
profile has distinct starting and
ending points to the ramp up.
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals the ISL6532A can achieve PGOOD status
significantly faster than other devices that depend on
Latched_Backfeed_Cut for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532A will disable the V
TT
linear regulator and the AGP
LDO controller. The V
DDQ
standby regulator will be enabled
ISL6532A
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相關代理商/技術參數(shù) |
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| ISL6532ACR-T | 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源管理 - 專用 系列:- 應用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:37 系列:- 應用:醫(yī)療用超聲波成像，聲納 電流 - 電源:- 電源電壓:2.37 V ~ 6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:56-WFQFN 裸露焊盤 供應商設備封裝:56-TQFN-EP（8x8） 包裝:管件 |
| ISL6532ACRZ | 功能描述:DC/DC 開關控制器 3-IN-1 DDRG W/NO OC FOR SPRINGDALE MBS RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| ISL6532ACRZ-T | 功能描述:DC/DC 開關控制器 3-IN-1 DDRG W/NO OC SPRINGDALE MBS 28L RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| ISL6532ACRZ-TK | 功能描述:DC/DC 開關控制器 3-IN-1 DDRG W/NO OC SPRINGDALE MBS 28L RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
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