
4
Functional Pin Description
VCC (Pin 1)
Provide a very well decoupled 5V bias supply for the IC to 
this pin by connecting it to the ATX 5V
SB
 output. This pin 
provides all the bias for the IC as well as the input voltage for 
the internal standby 3V3AUX LDO. The voltage at this pin is 
monitored for power-on reset (POR) purposes.
GND (Pin 5, Pad)
Signal ground for the IC. These pins are also the ground 
return for the internal 3V3AUX LDO that is active in 
S3/S4/S5 sleep states. All voltage levels are measured with 
respect to these pins.
S3# and S5# (Pins 3 and 4)
These pins switch the IC’s operating state from active (S0, 
S1/S2) to S3 and S4/S5 sleep states. These are digital 
inputs featuring internal 10
μ
A pull down current sources on 
each pin. Additional circuitry blocks illegal state transitions, 
such as S4/S5 to S3. Connect S3# and S5# to the computer 
system’s SLP_S3 and SLP_S5 signals, respectively.
3V3AUX (Pin 2)
Connect this pin to the 3V3DUAL output. In sleep states, the 
voltage at this pin is regulated to 3.3V through an internal 
pass device powered from 5VSBY through the VCC pin. In 
active states, ATX 3.3V output is delivered to this node 
through a fully-on NMOS transistor. During S3 and S4/S5 
states, this pin is monitored for undervoltage events.
DLA (Pin 6)
This pin is an open-drain output. A 1k
 resistor must be 
connected from this pin to the ATX 12V output. This resistor 
is used to pull the gates of suitable N-MOSFETs to 12V, 
which in active state, switch in the ATX 3.3V and 5V outputs 
into the 3.3V
AUX
 and 5V
DUAL
 outputs, respectively. This pin 
is also used to monitor the 12V rail during POR. If a resistor 
other than 1k
 is used, the POR level will be affected.
5VDLSB (Pin 7)
Connect this pin to the gate of a suitable P-MOSFET.
ISL6506 and ISL6506B: In S3 sleep state, this transistor is 
switched on, connecting the ATX 5V
SB
 output to the 5V
DUAL
regulator output. 
ISL6506A: In S3 and S4/S5 sleep state, this transistor is 
switched on, connecting the ATX 5V
SB
 output to the 5V
DUAL
regulator output.
Description
Operation
The ISL6506 controls 2 output voltages, 3.3V
DUAL
 and 
5V
DUAL
. It is designed for microprocessor computer 
applications requiring 3.3V, 5V, 5V
SB
, and 12V bias input 
from an ATX power supply. The IC is composed of one linear 
controller/regulator supplying the computer system’s 
3.3V
DUAL
 power, a dual switch controller supplying the 
5V
DUAL
 voltage, as well as all the control and monitoring 
functions necessary for complete ACPI implementation.
Initialization
The ISL6506 automatically initializes upon receipt of input 
power. The Power-On Reset (POR) function continually 
monitors the 5V
SB
 input supply voltage. The ISL6506 also 
monitors the 12V rail to insure that the ATX rails are up 
before entering into the S0 state even if both SLP_S3 and 
SLP_S5 are both high.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the 
3.3V
DUAL
 and 5V
DUAL 
outputs. The internal circuitry does 
not allow the transition from an S4/S5 state to an S3 state.
Functional Timing Diagrams
Figures 1 (ISL6506/B) and 2 (ISL6506A) are simplified timing 
diagrams, detailing the power up/down sequences of all the 
outputs in response to the status of the sleep-state pins (S3#, 
S5#), as well as the status of the input ATX supply. Not shown 
in these diagrams is the deglitching feature used to protect 
against false sleep state tripping. Additionally, the ISL6506 
features a 60
μ
s delay in transitioning from S0 to S3 states. The 
transition from the S0 state to S4/S5 state is immediate.
TABLE 1. 5V
DUAL
 OUTPUT TRUTH TABLE
S5
S3
3.3AUX
5VDL
COMMENTS
1
1
3.3V
5V
S0/S1/S2 States (Active)
1
0
3.3V
5V
S3
0
1
Note
Maintains Previous State
0
0
3.3V
0V
S4/S5 (ISL6506 & 06B)
0
0
3.3V
5V
S4/S5 (ISL6506A)
NOTE: Combination Not Allowed.
FIGURE 1. 5V
DUAL
 AND 3.3V
AUX
 TIMING DIAGRAM; 
ISL6506 and ISL6506B
5VSB
3.3V, 5V, 12V
S3
S5
5VDLSB
DLA
3V3AUX
5VDL
ISL6506, ISL6506A, ISL6506B