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參數(shù)資料
| 型號： | ISL6505CRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Multiple Linear Power Controller with ACPI Control Interface |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC20 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHC, QFN-20 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 371K |
| 代理商： | ISL6505CRZ |
10
are being supported. 3.3V
DUAL
/3.3V
SB
and V
OUT1
outputs
will come up right after bias voltage surpasses POR level
(but if LAN = GND, then V
OUT1
output will not come up until
the soft-start ramp, along with V
OUT2
; see Figure 9).
During sleep-to-active state transitions from conditions
where the 5V
DUAL
output is initially GND (such as S5 to S0
transition, or simple power-up sequence directly into active
state), the circuit goes through a quasi soft-start, the
5V
DUAL
output
being pulled high through the body diode of
the NMOS FET connected between it and the 5V ATX.
Figure 9 exemplifies this start-up case. 5V
SB
is already
present when the main ATX outputs are turned on, at time
T0. As a result of +5V
IN
ramping up, the 5V
DUAL
output
capacitors charge up through the body diode of Q5 (see
Typical Application). At time T1, all main ATX outputs
exceed the ISL6505’s undervoltage thresholds, and the
internal 50ms (typical) timer is initiated. At T2, the time-out
initiates a soft-start, and the 1.2V voltage ID output is
ramped-up, reaching regulation limits at time T3.
Simultaneous with the beginning of this ramp-up, at time T2,
the DLA pin is released, allowing the pull-up resistor to turn
on Q3 and Q5, and bring the 5V
DUAL
output in regulation.
Shortly after time T3, as the SS voltage reaches 3.0V, the
soft-start capacitor is quickly discharged down to
approximately 2.7V, where it remains until a valid sleep state
request is received from the system.
Fault Protection
All of the outputs are monitored against undervoltage
events. A severe overcurrent caused by a failed load on any
of the outputs, would, in turn, cause that specific output to
suddenly drop. If any of the output voltages drops below
80% (typical) of their set value, such event is reported by
having the FAULT pin pulled to 5V. Additionally, exceeding
the maximum current rating of an integrated regulator
(output with pass transistor on-chip) can lead to output
voltage drooping; if excessive, this droop can ultimately trip
the undervoltage detector and send a FAULT signal to the
computer system.
A FAULT condition occurring on an output when controlled
through an external pass transistor will only set off the
FAULT flag, and it will not shut off or latch off any part of the
circuit. A FAULT condition occurring on an output controlled
through an internal pass transistor (1V2VID only), will set off
the FAULT flag, and it will shut off the respective faulting
regulator (1V2VID only). If shutdown or latch off of the entire
circuit is desired in case of a fault, regardless of the cause,
this can be achieved by externally pulling or latching the SS
pin low. Pulling the SS pin low will also force the FAULT pin
to go low and reset any internally latched-off output.
Special consideration is given to the initial start-up
sequence. If, following a 5V
SB
POR event, any of the V
OUT1
or 3.3V
DUAL
/3.3V
SB
outputs is ramped up and is subject to
an undervoltage event before the end of the second soft-
start ramp, then the FAULT output goes high and the entire
IC latches off. Latch-off condition can be reset by cycling the
bias power (5V
SB
). Undervoltage events on the V
OUT1
and
the 3.3V
DUAL
/3.3V
SB
outputs at any other times are
handled according to the description found in the second
paragraph under the current heading.
Another condition that could set off the FAULT flag is chip
overtemperature. If the ISL6505 reaches an internal
temperature of 140
o
C (typical), the FAULT flag is set, but the
chip continues to operate until the temperature reaches
155
o
C (typical), when unconditional shutdown of all outputs
takes place. Operation resumes only after powering down
the IC (to create a 5V
SB
POR event) and a start-up
(assuming the cause of the fault has been removed; if not,
as it heats up again, it will repeat the FAULT cycle).
In ISL6505 applications, loss of the active ATX output (3V3
or 5V, as detected by the on-board voltage monitor) during
active state operation causes the chip to switch to S5 sleep
state, in addition to reporting the input UV condition on the
FAULT pin. Exiting from this forced S5 state can only be
achieved by returning the faulting input voltage above its UV
threshold, by resetting the chip through removal of 5V
SB
bias voltage, or by bringing the SS pin at a potential lower
than 0.8V.
FIGURE 9. SOFT-START INTERVAL IN ACTIVE STATE
0V
0V
TIME
OUTPUT
VOLTAGES
(1V/DIV)
T1
T2
T3
T0
INPUT VOLTAGES
(2V/DIV)
+5V
IN
+12V
IN
+5V
SB
V
OUT1
(LAN = 5V)
V
OUT3
(3.3V
DUAL
/3.3V
SB
)
V
OUT4
(5V
DUAL
)
DLA PIN
(2V/DIV)
+3.3V
IN
V
OUT2
(1.2V
VID
)
V
OUT1
(LAN = GND)
SOFT-START
(1V/DIV)
ISL6505
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