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參數(shù)資料
| 型號(hào)： | ISL6421A |
| 廠商： | Intersil Corporation |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 中文描述： | 單輸出LNB電源和控制穩(wěn)壓器，帶有I2C接口的先進(jìn)衛(wèi)星機(jī)頂盒設(shè)計(jì) |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 406K |
| 代理商： | ISL6421A |
9
FN9167.2
February 11, 2005
Received Data (
I
2
C
Bus Read Mode)
The ISL6421A can provide to the master a copy of the
System Register information via the I
2
C bus in read mode.
The read mode is Master activated by sending the chip
address with R/W bit set to 1. At the following Master
generated clock bits, the ISL6421A issues a byte on the
SDA data bus line (MSB transmitted first).
At the ninth clock bit the MCU master can:
Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6421A.
Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6421A.
Power-On I
2
C Interface Reset
The I
2
C interface built into the ISL6421A is automatically
reset at power-on. The I
2
C interface block will receive a
Power OK logic signal from the UVLO circuit. This signal will
go HIGH when chip power is OK. As long as this signal is
LOW, the interface will not respond to any I
2
C commands
and the system register SR is initialized to all zeros, thus
keeping the power blocks disabled.
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I
2
C interface block will be HIGH, the I
2
C
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.
(I
2
C comes up with EN = 0, EN goes HIGH at the same time
as (or later than) all other I
2
C data for the PWM becomes
valid).
ADDRESS Pin
Connecting this pin to GND forces the chip I
2
C interface
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
I
2
C Electrical Specifications
TABLE 6. READING SYSTEM REGISTERS
DCL ISEL ENT LLC VSEL EN OTF OLF
FUNCTION
These bits are read as they were
after the last write operation.
0
Tj
≤
130°C, Normal
operation
1
Tj > 150°C, Power
blocks disabled
0
Iout < Imax, Normal
operation
1
Iout > Imax, Overload
protection triggered
TABLE 7. ADDRESS PIN CHARACTERISTICS
Vaddr
MIN
TYP
MAX
Vaddr-1
“0001000”
0V
-
2.0V
Vaddr-2
“0001001”
2.7V
-
5.0V
TABLE 8. I
2
C SPECIFICATIONS
PARAMETER
TEST CONDITION
MINIMUM
TYPICAL
MAXIMUM
Input Logic High, VIH
SDA, SCL
0.7 x V
DD
Input Logic Low, VIL
SDA, SCL
0.3 x V
DD
Input Logic Current, IIL
SDA, SCL; 0.4V < Vin < 4.5V
10
μ
A
SCL Clock Frequency
0
100kHz
400kHz
NOTE: V
DD
= 5.0V/3.3V.
ISL6421A
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