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參數(shù)資料
| 型號(hào)： | ISL6421A |
| 廠商： | Intersil Corporation |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 中文描述： | 單輸出LNB電源和控制穩(wěn)壓器，帶有I2C接口的先進(jìn)衛(wèi)星機(jī)頂盒設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 406K |
| 代理商： | ISL6421A |
8
FN9167.2
February 11, 2005
Byte Format
Every byte put on the SDA line must be 8-bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull the SDA line
down (LOW) during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6421A will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6421A Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
A start condition (S)
A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I
2
C slave
address for the ISL6421A is 0001 00XX)
A sequence of data (1 byte + Acknowledge)
A stop condition (P)
System Register Format
R, W = Read and Write bit
R = Read-only bit
All bits reset to 0 at Power-On
Transmitted Data (
I
2
C
bus WRITE mode)
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR1/SR2)
of the ISL6421A via I
2
C bus. These will be written by the
microprocessor as shown below. The spare bits of SR1/SR2
can be used for other functions.
SDA
SCL
FIGURE 3. ACKNOWLEDGE ON THE I
2
C BUS
1
2
8
9
ACKNOWLEDGE
FROM SLAVE
MSB
START
TABLE 2. INTERFACE PROTOCOL
S
0
0
0
1
0
0
0
R/W ACK
Data (8 bits)
ACK P
TABLE 3. SYSTEM REGISTER 1 (SR1)
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R
SR1
DCL
X
ENT
LLC
VSEL
EN
OLF
TABLE 4. SYSTEM REGISTER 2 (SR2)
R, W
R, W
R, W
R, W
R, W
R, W
R
R
SR2
X
X
X
X
X
OTF
X
TABLE 5. SYSTEM REGISTER (SR1 AND SR2)
CONFIGURATION
SR DCL - ENT LLC VSEL EN OLF
FUNCTION
0
X
0
0
1
SR1 is selected
0
X
0
0
1
Vout1 = 13V,
Vboost1 = 13V + Vdrop
0
X
0
1
1
Vout1 = 18V,
Vboost1 = 18V + Vdrop
0
X
1
0
1
Vout1 = 14V,
Vboost1 = 14V + Vdrop
0
X
1
1
1
Vout1 = 19V,
Vboost1 = 19V + Vdrop
0
X
0
1
22kHz tone is controlled
by the DSQIN pin input
0
X
1
1
22kHz tone is ON,
DSQIN pin input is
disabled
0
1
X
1
Dynamic current limit
NOT selected
0
0
X
1
Dynamic current limit
selected
0
X
X
X
X
X
0
PWM and Linear for
channel 1 disabled
SR
-
-
-
-
-
OTF
-
FUNCTION
1
X
X
X
X
X
X
X
SR2 is selected; to read
OTF flag.
ISL6421A
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