參數(shù)資料
型號: ISL6223EVAL1
廠商: Intersil Corporation
英文描述: Mobile Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
中文描述: 移動微處理器核心電壓調(diào)節(jié)器的多相降壓PWM控制器
文件頁數(shù): 6/15頁
文件大?。?/td> 402K
代理商: ISL6223EVAL1
6
Operation
Figure 1 shows a simplified diagram of the voltage regulation
and current control loops. Both voltage and current feedback
are used to precisely regulate voltage and tightly control
output currents, I
L1
and I
L2
, of the two power channels. The
voltage loop comprises the Error Amplifier, Comparators,
gate drivers and output MOSFETs. The Error Amplifier is
essentially connected as a voltage follower that has an input,
the Programmable Reference DAC and an output that is the
CORE voltage.
Voltage Loop
Feedback from the CORE voltage is applied via resistor R
IN
to the inverting input of the Error Amplifier. This signal can
drive the Error Amplifier output either high or low, depending
upon the CORE voltage. Low CORE voltage makes the
amplifier output move towards a higher output voltage level.
Amplifier output voltage is applied to the positive inputs of
the Comparators via the Correction summing networks. Out-
of-phase sawtooth signals are applied to the two
Comparators inverting inputs. Increasing Error Amplifier
voltage results in increased Comparator output duty cycle.
This increased duty cycle signal is passed through the PWM
CIRCUIT with no phase reversal and on to the HIP6601,
again with no phase reversal for gate drive to the upper
MOSFETs, Q1 and Q3. Increased duty cycle or ON time for
the MOSFET transistors results in increased output voltage
to compensate for the low output voltage sensed.
Current Loop
The current control loop works in a similar fashion to the
voltage control loop, but with current control information
applied individually to each channel’s Comparator. The
information used for this control is the voltage that is
developed across r
DS(ON)
of each lower MOSFET, Q2 and
Q4, when they are conducting. A single resistor converts and
scales the voltage across the MOSFETs to a current that is
applied to the Current Sensing circuit within the ISL6223.
Output from these sensing circuits is applied to the current
averaging circuit. Each PWM channel receives the difference
current signal from the summing circuit that compares the
average sensed current to the individual channel current.
When a power channel’s current is greater than the average
current, the signal applied via the summing Correction circuit
to the Comparator, reduces the output pulse width of the
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6223 VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER
CHANNEL REGULATOR
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
+
R
ISEN1
+
CORRECTION
ERROR
AMPLIFIER
FB
REFERENCE
DAC
I
SEN1
R
IN
V
CORE
Q3
Q4
L
02
PHASE
PWM1
I
L2
ISL6223
C
OUT
R
LOAD
V
IN
HIP6601
-
Q1
Q2
L
01
PHASE
I
L1
V
IN
HIP6601
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
CORRECTION
PWM2
-
I AVERAGE
+
+
-
PROGRAMMABLE
R
ISEN2
I
SEN2
-
CURRENT
AVERAGING
+
-
+
-
+
-
ISL6223
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