
10
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID2, VID3 and
VID4) set the CORE output voltage. Each VID pin is pulled to
V
CC
by an internal 12
μ
A current source and accepts open-
collector/open-drain/open-switch-to-ground or standard low-
voltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is
±
1% accurate over
the operating temperature and voltage range.
Current Sensing and Balancing
Overview
The ISL6223 samples the on-state voltage drop across each
synchronous rectifier FET, Q2, as an indication of the
inductor current in that phase, see Figure 8. Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r
DS(ON)
(Q2) x inductor current (I
L
). Note that I
L
, the
inductor current, is 1/2 of the total current (I
LT
).
The voltage at Q2’s drain, the PHASE node, is applied to the
R
ISEN
resistor to develop the I
ISEN
current to the ISL6223
ISEN pin. This pin is held at virtual ground, so the current
through R
ISEN
is I
L
x r
DS(ON)
(Q2) / R
ISEN
.
The I
ISEN
current provides information to perform the
following functions:
1. Detection of an overcurrent condition
2. Reduce the regulator output voltage with increasing load
current (droop)
3. Balance the I
L
currents in the two phases
Overcurrent, Selecting R
ISEN
The current detected through the R
ISEN
resistor is averaged
with the current detected in the other channel. The averaged
current is compared with a trimmed, internally generated
current, and used to detect an overcurrent condition.
The nominal current through the R
ISEN
resistor should be
50
μ
A at full output load current, and the nominal trip point for
overcurrent detection is 150% of that value, or 75
μ
A.
Therefore, R
ISEN
= I
L
x
r
DS(ON)
(Q2) / 50
μ
A.
For a full load of 25A per phase, and an r
DS(ON)
(Q2) of
4m
, R
ISEN
= 2k
.
The overcurrent trip point would be 150% of 25A, or
approximately 37.5A per phase. The R
ISEN
value can be
adjusted to change the overcurrent trip point, but it is
suggested to stay within
±
25% of nominal.
Droop, Selection of R
IN
The average of the currents detected through the R
ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R
IN
, so the average
current creates a voltage drop across R
IN
. This drop increases
the apparent V
CORE
voltage with increasing load current,
causing the system to decrease V
CORE
to maintain balance at
the FB pin. This is the desired “droop” voltage used to maintain
V
CORE
within limits under transient conditions.
FIGURE 8. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
AVERAGING
CURRENT
SENSING
FROM
OTHER
CHANNEL
SAWTOOTH
GENERATOR
+
DIFFERENCE
R
ISEN
+
CORRECTION
ERROR
AMPLIFIER
FB
COMP
REFERENCE
DAC
TO OTHER
CHANNEL
I
SEN
R
IN
R
FB
C
c
V
CORE
Q1
Q2
COMPARATOR
REFERENCE
TO OVER
CURRENT
TRIP
L
01
PHASE
INDUCTOR
CURRENT
FROM
OTHER
CHANNEL
PWM
I
L
ISL6223
C
O
R
L
V
IN
ONLY ONE OUTPUT
STAGE SHOWN
HIP6601
-
-
+
-
+
-
+
-
ISL6223