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參數(shù)資料
| 型號(hào)： | ISL6208 |
| 廠商： | Intersil Corporation |
| 英文描述： | High Voltage Synchronous Rectified Buck MOSFET Driver(高電壓，同步整流降壓MOSFET驅(qū)動(dòng)器) |
| 中文描述： | 高電壓同步整流降壓MOSFET驅(qū)動(dòng)器（高電壓，同步整流降壓MOSFET的驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 1684K |
| 代理商： | ISL6208 |
8
FN9115.2
March 30, 2007
Layout Considerations
Reducing Phase Ring
The parasitic inductances of the PCB and power devices
(both upper and lower FETs) could cause increased PHASE
ringing, which may lead to voltages that exceed the absolute
maximum rating of the devices. When PHASE rings below
ground, the negative voltage could add charge to the
bootstrap capacitor through the internal bootstrap diode.
Under worst-case conditions, the added charge could
overstress the BOOT and/or PHASE pins. To prevent this
from happening, the user should perform a careful layout
inspection to reduce trace inductances, and select low lead
inductance MOSFETs and drivers. D
2
PAK and DPAK
packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must
be used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
A good layout would help reduce the ringing on the phase
and gate nodes significantly:
Avoid using vias for decoupling components where
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
Keep the connection in between the SOURCE of lower
FET and power ground wide and short.
Input capacitors should be placed as close to the DRAIN
of the upper FET and the SOURCE of the lower FET as
thermally possible.
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
ISL6208
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6208_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Voltage Synchronous Rectified Buck MOSFET Driver |
| ISL6208_11 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Voltage Synchronous Rectified Buck MOSFET Drivers |
| ISL6208_13 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Voltage Synchronous Rectified Buck MOSFET Drivers |
| ISL6208A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Voltage Synchronous Rectified Buck MOSFET Driver |
| ISL6208ACBZ | 功能描述:IC MOSFET DRVR SYNC BUCK 8-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:5 系列:- 配置:低端 輸入類型:非反相 延遲時(shí)間:600ns 電流 - 峰:12A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動(dòng)）:- 電源電壓:14.2 V ~ 15.8 V 工作溫度:-20°C ~ 60°C 安裝類型:通孔 封裝/外殼:21-SIP 模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名稱:835-1063 |
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