9
FN4901.3
January 19, 2010
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2) (Notes 7, 10) fCLK = 125MSPS, fOUT = 40.4MHz
-
40
-
dBc
fCLK = 125MSPS, fOUT = 10.1MHz
57
63
-
dBc
fCLK = 125MSPS, fOUT = 5.02MHz
-
72
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz
-
40
-
dBc
fCLK = 100MSPS, fOUT = 20.2MHz
-
49
-
dBc
fCLK = 100MSPS, fOUT = 5.04MHz
-
72
-
dBc
fCLK = 100MSPS, fOUT = 2.51MHz
-
73
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz
-
45
-
dBc
fCLK = 50MSPS, fOUT = 5.02MHz
-
68
-
dBc
fCLK = 50MSPS, fOUT = 2.51MHz
-
72
-
dBc
fCLK = 50MSPS, fOUT = 1.00MHz
-
71
-
dBc
fCLK = 25MSPS, fOUT = 1.0MHz
-
72
-
dBc
DAC REFERENCE VOLTAGE
Internal Reference Voltage, VFSADJ
Pin 13 Voltage with Internal Reference
1.13
1.2
1.28
V
Internal Reference Voltage Drift
-±60
-
ppm
/°C
Internal Reference Output Current
Sink/Source Capability
-±0.1
-
μA
Reference Input Impedance
-1
-
M
Ω
Reference Input Multiplying Bandwidth (Notes
7,
10)-
1.4
-
MHz
DIGITAL INPUTS
Input Logic High Voltage with
5V Digital Supply, VIH
3.5
5-
V
Input Logic High Voltage with
3V Digital Supply, VIH
2.0
3-
V
Input Logic Low Voltage with
5V Digital Supply, VIL
-
0
1.3
V
Input Logic Low Voltage with
3V Digital Supply, VIL
-
0
0.8
V
Input Logic Current, IIH
-10
-
+10
A
Input Logic Current, IIL
-10
-
+10
A
Digital Input Capacitance, CIN
-4
-
pF
TIMING CHARACTERISTICS
Maximum Clock Rate, fCLK
+5V DVDD, +5V AVDD (Note 6) 125
--
MSPS
Maximum Clock Rate, fCLK
+3.3V DVDD, +5V AVDD (Note 6) 100
--
MSPS
CLK Pulse Width, tCW
5
--
ns
Maximum Parallel Write Rate
Rate of WR pin
50
--
MSPS
WR Pulse Width, tWW
5
--
ns
Data Setup Time, tDS
Between DATA and WR (Note
6)10
--
ns
Data Hold Time, tDH
Between DATA and WR (Note
6)0
--
ns
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = -40°C to +85°C for
all Min and Max Values. TA = +25°C for All Typical Values. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
ISL5314