參數(shù)資料
型號(hào)： ISL5239EVAL1
廠商： Intersil Corporation
英文描述： Pre-Distortion Linearizer
中文描述： 預(yù)失真線性化電路
文件頁數(shù)： 29/31頁
文件大小： 653K
代理商： ISL5239EVAL1
29
TABLE 40. I-to-I (HM) COEFFICIENT
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x31
BIT
FUNCTION
DESCRIPTION
15:0
hm Coefficient
I-to-I (hm) coefficient values loaded from the master registers to the slave registers when the user writes
the last coefficient register in control word 0x38. The slave registers are used in the datapath. All reads
return slave register values. Default 1-2
(1-15)
.
TABLE 41. Q-to-I (KM) COEFFICIENT
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x32
BIT
FUNCTION
DESCRIPTION
15:0
km Coefficient
Q-to-I (km) master register. Default 0.
TABLE 42. I-to-Q (LM) COEFFICIENT
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x33
BIT
FUNCTION
DESCRIPTION
15:0
lm Coefficient
I-to-Q (lm) master register. Default 0.
TABLE 43. Q-toQ (GM) COEFFICIENT
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x34
BIT
FUNCTION
DESCRIPTION
15:0
Gm Coefficient
Q-to-Q (Gm) master register. Default 1-2
(1-15)
TABLE 44. I CHANNEL DC OFFSET MSW
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x35
BIT
FUNCTION
DESCRIPTION
15:4
Reserved
Not used.
3:0
DC I Offset <19:16>
I DC offset master register containing the upper four bits of the I DC offset.
TABLE 45. I CHANNEL DC OFFSET LSW
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x36
BIT
FUNCTION
DESCRIPTION
15:0
DC I Offset <15:0>
I DC offset master register containing the lower 16 bits of the I DC offset.
TABLE 46. Q CHANNEL DC OFFSET MSW
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x37
BIT
FUNCTION
DESCRIPTION
15:4
Reserved
Not used.
3:0
DC Q Offset <19:16>
Q DC offset master register containing the upper four bits of the Q DC offset.
TABLE 47. Q CHANNEL DC OFFSET LSW
TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x38
BIT
FUNCTION
DESCRIPTION
15:0
DC Q Offset <15:0>
Q DC offset master register containing the lower 16 bits of the Q DC offset.
ISL5239
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PDF描述
ISL5239 Pre-Distortion Linearizer
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ISL5239KIZ Pre-Distortion Linearizer
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