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參數(shù)資料
| 型號： | ISL5239EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Pre-Distortion Linearizer |
| 中文描述： | 預(yù)失真線性化電路 |
| 文件頁數(shù)： | 24/31頁 |
| 文件大小： | 653K |
| 代理商： | ISL5239EVAL1 |
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TABLE 15. MEMORY DATA LSW
TYPE: CAPTURE MEMORY, ADDRESS: 0x0c
BIT
FUNCTION
DESCRIPTION
15:0
Memory Data <15:0>
Lower 16 bits of capture memory data word.
TABLE 16. MEMORY DATA MSW
TYPE: CAPTURE MEMORY, ADDRESS: 0x0d
BIT
FUNCTION
DESCRIPTION
15:0
Memory Data <31:16>
Higher 16 bits of capture memory data word. Writing to this address triggers the write to the memory and
increments the address counter when address auto increment, control word 0x04, bit 13 is set. Must write
control word 0x0c first, to load the data values into memory.
TABLE 17. INPUT MEMORY STATUS
TYPE: CAPTURE MEMORY, ADDRESS: 0x0e
BIT
FUNCTION
DESCRIPTION
15:14
Reserved
Not used.
13:12
Input Capture Status
Read only register with status defined as:
00 - Idle, Memory access OK.
01 - Armed. Capture memory waiting for trigger.
10 - Loading. Capture memory in load mode.
11 - Send. Memory sends data to downstream modules.
10:0
Input Trigger Position
Read only register which records memory location of input trigger point. 2
0
to 2
11
(0...2047).
TABLE 18. FEEDBACK MEMORY STATUS
TYPE: CAPTURE MEMORY, ADDRESS: 0x0f
BIT
FUNCTION
DESCRIPTION
15:14
Reserved
Not used.
13:12
Feedback Capture Status Read only register with status defined as:
00 - Idle, Memory access OK.
01 - Armed. Capture memory waiting for trigger.
10 - Loading. Capture memory in load mode.
10
Reserved
Not used.
9:0
Feedback Trigger
Position
Read only register which records memory location of feedback trigger point. 2
0
to 2
10
(0...1023).
TABLE 19. CONTROL
TYPE: PRE-DISTORTER, ADDRESS: 0x10
BIT
FUNCTION
DESCRIPTION
15:3
Reserved
Not used.
2
Test
Selects use of test inputs
0 - Off. IIN<17:0>, QIN<17:0> in use for input stream.
1 - On. Use capture memory output for pre-Distorter input. Note: Test inputs are 16-bits wide and are MSB
justified onto the pre-distorter 20-bit inputs by setting the four LSB’s to zero.
1
Bypass
Disables processing and allows input data to flow to output without any pre-distorter modification.
0 - Pre-distorter is active and processing.
1 - Pre-distorter is bypassed.
0
Reset
Software generated logic reset, which when high, resets the pre-distorter circuitry. Low is default.
ISL5239
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